DMflag, below). The Kbus is a double height, extended length board. In addition, a special double height board must be connected at the opposite end of the Bus, to provide electrical termination.
Now that some basic modules have been described in detail we can illustrate how they function, when connected together by discussing the previous example in detail. The example is the one that was presented in Figure 6.
Notice that we have renamed the registers to correspond to the names used in the algorithm. For instance, the A and B registers of the DMgpa are renamed the I and S registers, respectively. The T(switch register) that is shown hasn't been described in detail yet, but it simply holds the value corresponding- to the binary switch value, and can be read, i.e.,<- N.
This particular implementation-operates as follows:
1. The power is turned on and all registers (except the manually set switches) are initialized to zero. This is carried out via the Bus POWER CLEAR line.
2. The manual START button is pressed and the Start control signal activates the first Ke module, which corresponds to the operation labeled I <- N. This module sends a <- N signal to the T(switch) and a I <- signal to the DMgpa.
3. Now the actual transfer is carried out under control of the Kbus, T(switch), and DMgpa. That is, the N register gates its stored information onto the Bus, and subsequently the DMgpa reads the information on the Bus into its I register. Notice that the Bus is fundamentally just a link (L), and not a register.
4. When the data transfer is completed, the first Ke receives the operation-complete signal (via DONE) and subsequently activates the- next Ke module, S<- 0.
5. The S <- 0 Ke module is now in control of the system and the cycle of evoking an operation is repeated for this module, causing 0 to be read into the S register of the DMgpa.
6. Control is passed on to the S <- S + I Ke, through a K(serial merge \Ksm) module. (Here a K(serial merge) allows control flow links to merge into a single link. A Ksm module is used whenever control paths for the same Bus are merged.)
7. The next Ke causes I to be decreased by 1 (i.e., I <- I - 1).
8. The I = 0 Kb2 module utilizes the fact-that the result of the previous register transfer is stored in the BSR register, which can be tested for 0. If the register is non-zero, control flow activates the serial merge causing the loop to be traversed again(steps 6, 7, and 8). When BSR = 0, the loop is terminated and the process stops.
Although the synchronization of the Bus transfers is invisible to the RT level designer-user, it operates as follows:
1. A Ke module is activated and given control of the system.
2. The Ke sends the evoke operation control signal to the sending and receiving DM, M, or T modules.
3. The sending module gates its information onto the Bus and puts a Bus DATA READY\DR signal on the Bus.
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