266 THE PDP-11 FAMILY

Since the performance of cache memory is a function not only of cache organization parameters but also of the program run, it is desirable to run cache simulations with a wide variety of programs. Multiplying these by a wide variety of a cache's organizational parameters to be simulated resulted in a considerable amount of simulation data of which only the highlights are reported here.

The first experiment was to determine the approximate overall size of the cache memory. Plots of the miss ratio against cache size for several programs* are given in Figure 2. (All sizes in both the figures and the discussion are 16-bit PDP-l 1 words.) A block size of two and a set size of one were held constant. In general, the miss ratio falls rapidly for caches up to 1024 words and falls less rapidly thereafter.

Figure 3 depicts the effect of set size (associativity) on cache performance. In order to clarify the results, Figures 3 through 6 only contain simulation data for a single program (the Macro assembler) which had the highest miss ratio in Figure 2. As expected, a larger set size reduces the miss ratio. The largest improvement occurs in going from set size one to set size two. Although not shown, even going to fully associative cache has little further effect on the miss ratio.

Figure 2. Effect of cache size on miss ratio.

Figure 3. Effect of set size on miss ratio.

Figure 4. Effect of block size on miss ratio.

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* These programs are system and user programs running under the PDP-l 1 DOS operating system. They include a Macro assembler, FORTRAN compiler, PIP (a file utility program), and FORTRAN executions of numerical applications. The range of miss ratios is typical for the much wider group of programs actually simulated. Indeed, the miss ratio for the Macro assembler for a given cache size was the worst of any program simulated.