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CACHE MEMORIES FOR PDP-1 1 FAMILY COMPUTERS 267

Figure 5. Effect of replacement algorithm and write allocation on miss ratio.

In Figure 4, the impact of block size is shown. Especially in smaller caches, going to a larger block significantly reduces the miss ratio. This is a result of a smaller cache depending more on the pre-fetching effect for its performance.

The effect of write allocation and replacement algorithm is given in Figure 5. For the program considered, there is a negligible performance difference across the different strategies.

In Figure 6, the effect of periodically clearing the cache is depicted. This approximates the effect on the cache of rapid context switching in that, when a new program is brought in, the cache appears "clear" to it. Even completely clearing the cache every 300 Pc accesses only degrades the miss ratio to 0.3. This represents a worst case condition that would be unrealized in practice. For example, the "new program" brought in every 300 Pc references might be an

Figure 6. Effect of clear interval on miss ratio.

interrupt handler. Any program running that often would typically find that the cache always contained information relevant to it. Indeed, for the cache organization given, it is impossible in 300 accesses to significantly clear a 1024- word cache.

CONCLUSIONS

The performance goals of the PDP-l 1/70 computer system required the typical miss ratio to be 0.1 or less. Analysis of the preceding data, with emphasis on the breaks in the curves, suggested that the optimal organization was a cache size of 1024 words, block size of two words, and a set size of two. Because the data suggests that the replacement algorithm and write allocation strategies have negligible effect, a no-write-allocate strategy and a random replacement algorithm were selected.

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