TMbox: A Flexible and Reconfigurable 16-core Hybrid Transactional Memory System
- Nehir Sonmez ,
- Oriol Arcas ,
- Otto Pflucker ,
- Osman S. Unsal ,
- Adri´an Cristal ,
- Ibrahim Hur ,
- Satnam Singh ,
- Mateo Valero
FPGAs for Custom Computing Machines 2011 |
Published by IEEE Computer Society
In this paper we present the design and implementation of TMbox: An MPSoC built to explore tradeoffs in multicore design space and to evaluate parallel programming proposals such as Transactional Memory (TM). Our flexible system, comprised of MIPS R3000-compatible cores is easily modifiable to study different architecture, library and operating system extensions. For this paper we evaluate a 16-core Hybrid Transactional Memory implementation based on the TinySTMASF proposal on a Virtex-5 FPGA and we accelerate three benchmarks written to investigate TM.