Publications

Refereed Publications

    2008

  1. Thomas Moscibroda and Onur Mutlu,
    "Distributed Order Scheduling and its Application to Multi-Core DRAM Controllers"
    to appear in Proceedings of the 27th Symposium on Principles of Distributed Computing (PODC), Toronto, ON, Canada, August 2008.
  2. Onur Mutlu and Thomas Moscibroda,
    "Parallelism-Aware Batch Scheduling: Enhancing both Performance and Fairness of Shared DRAM Systems"
    to appear in Proceedings of the 35th International Symposium on Computer Architecture (ISCA), Beijing, China, June 2008.
  3. Engin Ipek, Onur Mutlu, José F. Martínez, and Rich Caruana,
    "Self Optimizing Memory Controllers: A Reinforcement Learning Approach"
    to appear in Proceedings of the 35th International Symposium on Computer Architecture (ISCA), Beijing, China, June 2008.
  4. José A. Joao, Onur Mutlu, Hyesoon Kim, Rishi Agarwal, and Yale N. Patt,
    "Improving the Performance of Object-Oriented Languages with Dynamic Predication of Indirect Jumps"
    Proceedings of the 13th International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS), pages 80-90, Seattle, WA, March 2008. Slides (pptx)
  5. Chang Joo Lee, Hyesoon Kim, Onur Mutlu, and Yale N. Patt,
    "Performance-Aware Speculation Control using Wrong Path Usefulness Prediction"
    Proceedings of the 14th International Symposium on High-Performance Computer Architecture (HPCA), pages 39-49, Salt Lake City, UT, February 2008. Slides (ppt)

    6. 2007

  6. Onur Mutlu and Thomas Moscibroda,
    "Stall-Time Fair Memory Access Scheduling for Chip Multiprocessors"
    Proceedings of the 40th International Symposium on Microarchitecture (MICRO), pages 146-158, Chicago, IL, December 2007. Slides (ppt)
  7. Kypros Constantinides, Onur Mutlu, Todd Austin, and Valeria Bertacco,
    "Software-Based Online Detection of Hardware Defects: Mechanisms, Architectural Support, and Evaluation"
    Proceedings of the 40th International Symposium on Microarchitecture (MICRO), pages 97-108, Chicago, IL, December 2007. Slides (ppt)
  8. Thomas Moscibroda and Onur Mutlu,
    "Memory Performance Attacks: Denial of Memory Service in Multi-Core Systems"
    Proceedings of the 16th USENIX Security Symposium (USENIX SECURITY), pages 257-274, Boston, MA, August 2007. Slides (ppt)
  9. Hyesoon Kim, José A. Joao, Onur Mutlu, Chang Joo Lee, Yale N. Patt, and Robert S. Cohn,
    "VPC Prediction: Reducing the Cost of Indirect Branches via Hardware-Based Dynamic Devirtualization"
    Proceedings of the 34th International Symposium on Computer Architecture (ISCA), pages 424-435, San Diego, CA, June 2007. Slides (ppt)
    An extended version including evaluation of object-oriented Java applications, as HPS Technical Report, TR-HPS-2007-002, University of Texas at Austin, March 2007.
  10. José A. Joao, Onur Mutlu, Hyesoon Kim, and Yale N. Patt,
    "Dynamic Predication of Indirect Jumps"
    IEEE Computer Architecture Letters (CAL), Vol. 6, May 2007.
  11. Hyesoon Kim, José A. Joao, Onur Mutlu, and Yale N. Patt,
    "Profile-assisted Compiler Support for Dynamic Predication in Diverge-Merge Processors"
    Proceedings of the 5th International Symposium on Code Generation and Optimization (CGO), pages 367-378, San Jose, CA, March 2007. Slides (ppt)
  12. Santhosh Srinath, Onur Mutlu, Hyesoon Kim, and Yale N. Patt,
    "Feedback Directed Prefetching: Improving the Performance and Bandwidth-Efficiency of Hardware Prefetchers"
    Proceedings of the 13th International Symposium on High-Performance Computer Architecture (HPCA), pages 63-74, Phoenix, AZ, February 2007. Slides (ppt)
    One of the five papers nominated for the Best Paper Award by the Program Committee.
  13. Hyesoon Kim, José A. Joao, Onur Mutlu, and Yale N. Patt,
    "Diverge-Merge Processor: Generalized and Energy-Efficient Dynamic Predication"
    IEEE Micro, Special Issue: Micro's Top Picks from 2006 Computer Architecture Conferences (MICRO TOP PICKS), Vol. 27, No. 1, pages 94-104, January/February 2007.

    14. 2006

  14. Hyesoon Kim, José A. Joao, Onur Mutlu, and Yale N. Patt,
    "Diverge-Merge Processor (DMP): Dynamic Predicated Execution of Complex Control-Flow Graphs Based on Frequently Executed Paths"
    Proceedings of the 39th International Symposium on Microarchitecture (MICRO), pages 53-64, Orlando, FL, December 2006. Slides (ppt)
    One of the 11 computer architecture papers of 2006 selected as Top Picks by IEEE Micro.
    Nominated for the Best Paper Award.
    An extended version as HPS Technical Report, TR-HPS-2006-008, University of Texas at Austin, September 2006.
  15. Onur Mutlu, Hyesoon Kim, and Yale N. Patt,
    "Address-Value Delta (AVD) Prediction: A Hardware Technique for Efficiently Parallelizing Dependent Cache Misses"
    IEEE Transactions on Computers (TC), Vol. 55, No. 12, pages 1491-1508, December 2006.
  16. Moinuddin K. Qureshi, Daniel N. Lynch, Onur Mutlu, and Yale N. Patt,
    "A Case for MLP-Aware Cache Replacement"
    Proceedings of the 33rd International Symposium on Computer Architecture (ISCA), pages 167-177, Boston, MA, June 2006. Slides (ppt)
  17. Hyesoon Kim, M. Aater Suleman, Onur Mutlu, and Yale N. Patt,
    "2D-Profiling: Detecting Input-Dependent Branches with a Single Input Data Set"
    Proceedings of the 4th International Symposium on Code Generation and Optimization (CGO), pages 159-169, New York, NY, March 2006. Slides (ppt) Slides (pdf)
    An extended version as HPS Technical Report, TR-HPS-2006-001, University of Texas at Austin, January 2006.
  18. Onur Mutlu, Hyesoon Kim, and Yale N. Patt,
    "Efficient Runahead Execution: Power-Efficient Memory Latency Tolerance"
    IEEE Micro, Special Issue: Micro's Top Picks from Microarchitecture Conferences (MICRO TOP PICKS), Vol. 26, No. 1, pages 10-20, January/February 2006. Submitted final version
  19. Hyesoon Kim, Onur Mutlu, Jared Stark, and Yale N. Patt,
    "Wish Branches: Enabling Adaptive and Aggressive Predicated Execution"
    IEEE Micro, Special Issue: Micro's Top Picks from Microarchitecture Conferences (MICRO TOP PICKS), Vol. 26, No. 1, pages 48-58, January/February 2006. Submitted final version

    20. 2005

  20. Onur Mutlu, Hyesoon Kim, David N. Armstrong, and Yale N. Patt,
    "An Analysis of the Performance Impact of Wrong-Path Memory References on Out-of-Order and Runahead Execution Processors"
    IEEE Transactions on Computers (TC), Vol. 54, No. 12, pages 1556-1571, December 2005.
  21. Onur Mutlu, Hyesoon Kim, and Yale N. Patt,
    "Address-Value Delta (AVD) Prediction: Increasing the Effectiveness of Runahead Execution by Exploiting Regular Memory Allocation Patterns"
    Proceedings of the 38th International Symposium on Microarchitecture (MICRO), pages 233-244, Barcelona, Spain, November 2005. Slides (ppt) Slides (pdf)
    One of the five papers nominated for the Best Paper Award by the Program Committee.
    An extended version as HPS Technical Report, TR-HPS-2006-004, University of Texas at Austin, April 2006.
  22. Hyesoon Kim, Onur Mutlu, Jared Stark, and Yale N. Patt,
    "Wish Branches: Combining Conditional Branching and Predication for Adaptive Predicated Execution"
    Proceedings of the 38th International Symposium on Microarchitecture (MICRO), pages 43-54, Barcelona, Spain, November 2005. Slides (ppt)
    One of the 13 computer architecture papers of 2005 selected as Top Picks by IEEE Micro.
  23. Onur Mutlu, Hyesoon Kim, David N. Armstrong, and Yale N. Patt,
    "Using the First-Level Caches as Filters to Reduce the Pollution Caused by Speculative Memory References"
    International Journal of Parallel Programming (IJPP), Vol. 33, No. 5, pages 529-559, October 2005.
  24. Onur Mutlu, Hyesoon Kim, and Yale N. Patt,
    "Techniques for Efficient Processing in Runahead Execution Engines"
    Proceedings of the 32nd International Symposium on Computer Architecture (ISCA), pages 370-381, Madison, WI, June 2005. Slides (ppt) Slides (pdf)
    One of the 13 computer architecture papers of 2005 selected as Top Picks by IEEE Micro.
  25. Moinuddin K. Qureshi, Onur Mutlu, and Yale N. Patt,
    "Microarchitecture-Based Introspection: A Technique for Transient-Fault Tolerance in Microprocessors"
    Proceedings of the International Conference on Dependable Systems and Networks (DSN), pages 434-443, Yokohama, Japan, June 2005. Slides (pdf)
  26. Onur Mutlu, Hyesoon Kim, Jared Stark, and Yale N. Patt,
    "On Reusing the Results of Pre-Executed Instructions in a Runahead Execution Processor"
    IEEE Computer Architecture Letters (CAL), Vol. 4, January 2005.

    27. 2004

  27. David N. Armstrong, Hyesoon Kim, Onur Mutlu, and Yale N. Patt,
    "Wrong Path Events: Exploiting Unusual and Illegal Program Behavior for Early Misprediction Detection and Recovery"
    Proceeedings of the 37th International Symposium on Microarchitecture (MICRO), pages 119-128, Portland, OR, December 2004. Slides (pdf) Slides (ppt)
    An extended version as HPS Technical Report, TR-HPS-2004-002, University of Texas at Austin, June 2004.
  28. Onur Mutlu, Hyesoon Kim, David N. Armstrong, and Yale N. Patt,
    "Cache Filtering Techniques to Reduce the Negative Impact of Useless Speculative Memory References on Processor Performance"
    Proceeedings of the 16th Symposium on Computer Architecture and High Performance Computing (SBAC-PAD), pages 2-9, Foz Do Iguacu, PR, Brazil, October 2004. Slides (pdf)
  29. Onur Mutlu, Hyesoon Kim, David N. Armstrong, and Yale N. Patt,
    "Understanding the Effects of Wrong-Path Memory References on Processor Performance"
    Proceedings of the 3rd Workshop on Memory Performance Issues (WMPI), pages 56-64, Munchen, Germany, June 2004. Slides (pdf)
    An extended version as HPS Technical Report, TR-HPS-2005-001, University of Texas at Austin, January 2005.

    30. 2003

  30. Onur Mutlu, Jared Stark, Chris Wilkerson, and Yale N. Patt,
    "Runahead Execution: An Effective Alternative to Large Instruction Windows"
    IEEE Micro, Special Issue: Micro's Top Picks from Microarchitecture Conferences (MICRO TOP PICKS), Vol. 23, No. 6, pages 20-25, November/December 2003.
  31. Onur Mutlu, Jared Stark, Chris Wilkerson, and Yale N. Patt,
    "Runahead Execution: An Alternative to Very Large Instruction Windows for Out-of-order Processors"
    Proceedings of the 9th International Symposium on High-Performance Computer Architecture (HPCA), pages 129-140, Anaheim, CA, February 2003. Slides (pdf)
    One of the 15 computer architecture papers of 2003 selected as Top Picks by IEEE Micro.

Dissertation

Technical Reports

  1. Hyesoon Kim, José A. Joao, Onur Mutlu, Chang Joo Lee, Yale N. Patt, and Robert S. Cohn
    "VPC Prediction: Reducing the Cost of Indirect Branches via Hardware-Based Dynamic Devirtualization"
    HPS Technical Report, TR-HPS-2007-002, March 2007.
  2. Thomas Moscibroda and Onur Mutlu,
    "Memory Performance Attacks: Denial of Memory Service in Multi-Core Systems"
    Microsoft Research Technical Report, MSR-TR-2007-15, February 2007.
  3. Chang Joo Lee, Hyesoon Kim, Onur Mutlu, and Yale N. Patt,
    "A Performance-Aware Speculation Control Technique Using Wrong Path Usefulness Prediction"
    HPS Technical Report, TR-HPS-2006-010, December 2006.
  4. Hyesoon Kim, José A. Joao, Onur Mutlu, and Yale N. Patt,
    "Diverge-Merge Processor (DMP): Dynamic Predicated Execution of Complex Control-Flow Graphs Based on Frequently Executed Paths"
    HPS Technical Report, TR-HPS-2006-008, September 2006.
  5. Santhosh Srinath, Onur Mutlu, Hyesoon Kim, and Yale N. Patt,
    "Feedback Directed Prefetching: Improving the Performance and Bandwidth-Efficiency of Hardware Prefetchers"
    HPS Technical Report, TR-HPS-2006-006, May 2006.
  6. Hyesoon Kim, José A. Joao, Onur Mutlu, and Yale N. Patt,
    "Compiler-Assisted Dynamic Predicated Execution of Complex Control-Flow Structures"
    HPS Technical Report, TR-HPS-2006-005, April 2006.
  7. Onur Mutlu, Hyesoon Kim, and Yale N. Patt,
    "Address-Value Delta (AVD) Prediction: A Hardware Technique for Efficiently Parallelizing Dependent Cache Misses"
    HPS Technical Report, TR-HPS-2006-004, April 2006.
  8. Moinuddin K. Qureshi, Daniel N. Lynch, Onur Mutlu, and Yale N. Patt,
    "A Case for MLP-Aware Cache Replacement"
    HPS Technical Report, TR-HPS-2006-003, University of Texas at Austin, February 2006.
  9. Hyesoon Kim, M. Aater Suleman, Onur Mutlu, and Yale N. Patt,
    "2D-Profiling: Detecting Input-Dependent Branches with a Single Input Data Set"
    HPS Technical Report, TR-HPS-2006-001, University of Texas at Austin, January 2006.
  10. Hyesoon Kim, Onur Mutlu, Jared Stark, David N. Armstrong, and Yale N. Patt,
    "Wish Branch: A New Control Flow Instruction Combining Conditional Branching and Predicated Execution"
    HPS Technical Report, TR-HPS-2005-002, University of Texas at Austin, February 2005.
  11. Onur Mutlu, Hyesoon Kim, David N. Armstrong, and Yale N. Patt,
    "An Analysis of the Performance Impact of Wrong-Path Memory References on Out-of-Order and Runahead Execution Processors"
    HPS Technical Report, TR-HPS-2005-001, University of Texas at Austin, January 2005.
  12. Moinuddin K. Qureshi, Onur Mutlu, and Yale N. Patt,
    "Microarchitecture-Based Introspection: A Technique for Transient-Fault Tolerance in Microprocessors"
    HPS Technical Report, TR-HPS-2004-004, University of Texas at Austin, December 2004.
  13. David N. Armstrong, Hyesoon Kim, Onur Mutlu, and Yale N. Patt,
    "Wrong Path Events: Exploiting Illegal and Unusual Program Behavior for Early Misprediction Recovery"
    HPS Technical Report, TR-HPS-2004-002, University of Texas at Austin, June 2004.

Patents

  1. Onur Mutlu, Jared Stark, and Chris Wilkerson,
    "Apparatus for Memory Communication During Runahead Execution"
    Under review, filed December 2002.
  2. Onur Mutlu and Eric Sprangle,
    "Method and Apparatus to Control Memory Accesses"
    US Patent 6,799,257. Granted September 28, 2004. Filed February 21, 2002. Assignee: Intel Corporation

Project Reports

  1. Hyesoon Kim, Onur Mutlu, and Santhosh Srinath,
    "The Design of a 7-stage Pipelined 143 MHz Microprocessor Implementing a Subset of the x86 ISA"
    EE 382N (Microarchitecture) Project Report, University of Texas at Austin, May 2002.
  2. Onur Mutlu,
    "An Overview of Image Watermarking Algorithms"
    EE 371R (Digital Image and Video Processing) Project Report, University of Texas at Austin, December 2001.
  3. Onur Mutlu and Chandresh Jain,
    "Effectiveness of TCP for Video Transport"
    CS 384V (Multimedia Systems) Project Report, University of Texas at Austin, November 2001.
  4. Onur Mutlu and Aditya Bhattacharya,
    "Alpha 21264 Microarchitecture"
    EE 382N (Superscalar Microprocessor Architecture) Slides, University of Texas at Austin, November 2001.
  5. Chandresh Jain and Onur Mutlu,
    "Design of a Buffer Management Scheme for Video Servers"
    CS 384V (Multimedia Systems) Project Report, University of Texas at Austin, October 2001.
  6. Onur Mutlu,
    "Memory Dependence Prediction and Access Ordering for Memory Disambiguation and Renaming"
    EE 382N (Superscalar Microprocessor Architecture) Literature Survey, University of Texas at Austin, October 2001.
  7. Yousuf Ahmed, Chandresh Jain, and Onur Mutlu,
    "A Global Predicate Detector for Distributed Computation"
    EE 382N (Distributed Systems) Project Report, Winner of Best Project Award, University of Texas at Austin, December 2000.
  8. Onur Mutlu,
    "Effects of the Type of Loud Background Music on Speed of Processing"
    PSYCH 341 (Cognitive Psychology Laboratory) Project Report, University of Michigan, Ann Arbor, August 2000.
  9. Nai Ka Chung, Tufan C. Karalar, Pak Hei M. Leung, Onur Mutlu, and Cheongyuen Tsang,
    "A Low-Power Low-Cost 16-Bit RISC Microcontroller for Security Systems"
    EECS 427 (VLSI Design) Project Report, University of Michigan, Ann Arbor, April 2000. Chip Image
  10. Onur Mutlu,
    "A Grammatical Sketch of Even"
    LING 112 (Languages of the World) Project Report, University of Michigan, Ann Arbor, December 1999.