422 Part 5 The PMS level
Section 2 ÷ Computers with one central processor and multiple input/output processors
Fig. 1. The Stretch system.
data-word rate is achieved by the use of four modulo-4 organized memories. The addressing of the memories and the transfer of information from and to the memories by a memory bus permits new addresses, information, or both to pass through the bus every 200 mm sec.
b The simultaneously-operating Input/Output units are linked with the memories and the computer through the Exchange, which, after initial instruction by the computer, coordinates the starting of the I/O equipment, the checking and error-correction of the information, the arrangement of the information into memory words, and the fetching and storing of the information from and to memory. All these functions are executed without the use of the computer, so it can in the meantime continue its data processing and computation.
c The central computer processes and executes the stored program. Here, now, the simultaneity and multiplexing of functions has reached its ultimate.
Before discussing the computer organization, a few general features must be mentioned for completeness:
a Word length: 64 bits plus eight bits for parity checks and error-correction codes.
b Memory capacity and addressing: A possible 256,000 words can be randomly addressed. These storage positions are all in external memory, except for the 32 first addresses. These positions consist of the internal registers (accumulators, time clocks, index registers).
c The instructions are single-address instructions with the exception of a number of special codes that imply the second address explicitly.
The instruction set (Fig. 2) is generalized and contains a full set for single- and double-precision floating-point arithmetic, and a full set for variable-field-length integer arithmetic (binary and decimal). It also has a generalized set for index modification and a branching set, as well as a set of