Chapter 28 Microprogramming and the design of the control circuits in an electronic digital computer 337
make the output from the decoding tree branch before it enters matrix A so that the nature of the micro-operation that is performed depends on the setting of the conditional flip-flop.
The micro-programme wired on to the matrices contains sections for performing the operations required by each order in the basic order code of the machine. To initiate the operation it is only necessary that control in the micro-programme should be sent to the correct entry point. This is done by placing the function digits of the order in the least significant part of register II, the other digits in this register being made zero. The micro-programme is constructed so that when this number passes into register I, control in the micro-programme is sent to the correct entry point.
The switching system in the arithmetical unit may either be designed to permit a large variety of micro-operations to be performed, or it may be restricted so as to allow only a small number of such operations. In a machine with a comprehensive order code there is much to be said for having the more flexible switching system since this will enable an economy to be made in the number of micro-orders needed in the micro-programme.
A similar remark applies in connexion with the degree of flexibility to be provided when designing the switching system for the control register unit. If the specification of the machine allows the same number of registers to be used in the arithmetical and control sections, the construction of these two sections may be identical except as far as the number of digits is concerned. In a new machine under construction in the Mathematical Laboratory, Cambridge, the registers are being constructed in basic units each containing five registers and an adder-subtractor together with the associated switching system. It is hoped that it will be possible to use identical units in the arithmetical unit and in the control register unit.
3. Example
An example will now be given to show the way in which a micro-programme can be drawn up for a machine with a single-address order code covering the usual operations. It is supposed that the arithmetical unit contains the following registers:
A multiplicand register
B accumulator (least significant half)
C accumulator (most significant half)
D shift register
The registers in the control register unit are as follows:
E register connected to the access circuits of the store; the address of a storage location to which access is required is placed here
F sequence control register; contains address of next order due to be executed
C register used for counting
It was assumed when drawing up the micro-programme that there was an adder-subtractor in the arithmetical unit with one input permanently connected to register D, and a similar adder-subtractor in the control register unit with one input permanently connected to register C. For convenience it was assumed that the switching systems in each case were comprehensive enough to provide any micro-operation required. It was further supposed that the arithmetical unit provided for 20 digits and that the numbers 0, 1 and 18 could be introduced at will into one of the registers or the adder of the control register unit. Two conditional flip-flops are used. All micro-operations including those involving access to the store are supposed to take the same amount of time. Reference will be made to this point in ~4.
Table 1 gives the order code of the machine, and Table 2 the micro-programme. Each line of Table 2 refers to one micro-order; the first column gives the address of the micro-order, the second column specifies the micro-operations called for in the arithmetical unit of the machine, and the third column specifies the micro-
Table 1
|
Notation: Acc = accumulator Acc1 = most significant half of accumulator Acc2 = least significant half of accumulator n = storage location n C(X) = contents of X (X = register or storage location) |
||
|
Order |
Effect of order |
|
|
A n |
C(Acc) + C(n) to Acc |
|
|
S n |
C(Acc) - C(n) to Acc |
|
|
H n |
C(n) to Acc2 |
|
|
V n |
C(Acc2) . C(n) to Acc, where C(n) > 0 |
|
|
T n |
C(Acc1) to n, 0 to Acc |
|
|
Un |
C(Acc1) to n |
|
|
R n |
C(Acc) . 2-(n+1) to Acc |
|
|
L n |
C(Acc) . 2n+1 to Acc |
|
|
G n |
If C(Acc) < 0, transfer control to n; if C(Acc) > 0, ignore (i.e., proceed serially) |
|
|
I n |
Read next character on input mechanism into n |
|
|
0 n |
Send C(n) to output mechanism |
|