Chapter 7 Some aspects of the logical design of a control computer: a case study 155

algorithm more efficient than a nonrestoring one. The quotient delivered to A has a sign determined according to normal algebraic rules by the signs of (A) and (K); the same sign is available in LP to aid in determining the correct sign of the remainder from those of the divisor and quotient in case the quotient has been absorbed by subsequent processing. DV is not usually indexed, but it pays such large benefits in space and time, especially in double-precision division, that the cost of extracode indexing is negligible. If the divisor is less in magnitude than the dividend, or is zero, the quotient has correct sign and, in general, maximum magnitude. No infinite loop results in any case.

The primary justification for this instruction is that it allows multiple-precision addition subroutines to be changed into multiple-precision subtract subroutines merely by changing the indexing quantity. There are occasions in the middle of involved calculations where it is clumsy to construct a subtraction out of complementations and additions, especially when the sign of an overflow is of interest. Since SU differs from AD only in that the operand from memory is read out of the complement side of the buffer register B rather than the direct side, its cost is virtually zero. This last is not necessarily true when using core-transistor logic, or two's complement notation.

The AGC's 12-bit address field is insufficient for specifying directly all the registers in its memory. This predicament seems increasingly to afflict most computers, either because indirect addressing is assumed as a necessary evil from the start or, as was our case, because our earliest estimates of memory requirements were wrong by a factor of two or three. The method of indirect addressing we arrived at uses a bank register MB, but with an important modification: the 5-bit number stored in MB has no effect unless the address is in the range (octal) 6000 to 7777. The MB register contents are not interpreted as higher-order bits of the address; they are interpreted as integers which specify which bank of 1024 words is meant in the event of the address part of the instruction being in the ambiguous range. The over-all map of memory is shown in Table 2. The unambiguous, fixed memory addresses domain has come to be known as "fixed-fixed."

It is interesting that this method of extending the addressing capability was not the result of trying to improve upon more conventional methods, but was almost a consequence of the phys

ical difference between fixed and erasable memory. Since all data other than constants are concentrated in the erasable memory, these had to be exempt from modification by the MB register. An alternative arrangement, whereby only the addresses of instructions (as opposed to the addresses within an instruction word) are modified, would be deficient in that it would allow only instructions to be stored in banks; there would be no way to refer to constants stored in banks, or to use bank addresses to store arguments of arithmetic operations. The possibility of using two bank registers is worthy of serious consideration [Casale, 1962], but it did not occur to us.

In addition to the addresses in erasable, it is necessary to exempt the addresses of interrupting programs (i.e., the addresses to which a program interrupt transfers control) from the influence of the MB register. It was clear that it would be valuable to have a large body of unambiguous addresses for use in executive and dispatcher programs.

The most frequent and critical applications of bank changing are in the AGC's interpretive mode. Most of the programs relevant to navigation are written in a parenthesis-free pseudocode notation for economy of storage. An interpretive program executes these pseudocode programs by performing the indicated data accesses and subroutine linkages.

The format of the notation permits two macrooperators (e.g., "double-precision vector dot product") or one data address to be stored in one AGC word. Thus data addresses appear as full 15-bit words, potentially capable of addressing up to 32,768 registers. Each such address is examined in the interpreter and the contents of the bank register are changed if necessary; preparation is also made for subsequent return if a subroutine call is being made.

The structure of the interpretive program, and its relationship to the computer characteristics discussed in this paper will not be taken up here except to point out that parenthesis-free notation is particularly valuable in a short-word computer such as the AGC. It permits a very substantial expansion of the address and pseudo-operation fields without sacrificing efficiency in program storage [Muntz, 1962].