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reading or writing of a given word in Mp. The range of complexity is roughly

An S.duplex can be used to increase the number of processors that can be connected to the memory system while not having to provide additional switch points on each memory. For example, in the CDC 3600 [Casale, 1962] a basic S[8M; 4P; concurrency :4] is expanded by placing another S [1M; 6P; concurrency : 1] in series to give a possible overall S[8M; 24P; concurrency : 4]. This scheme was used to provide multiple processor accesses to the memories.

The first switching problem developed with the need to communicate with several input/output devices. This switching is hierarchical in nature; one (or two) processors maintain control of many K's by issuing K a primitive task. At the completion of the task the K signals the processor that the task has been completed.

The switch provides a link between processor and controls for the secondary memory or the terminals and is parameterized by the number of processors, the number of controls, the number of simultaneous conversations, and the component that originates the dialogue. In these switches the control of information transmission is always by the processor. The evolution has been approximately as follows:

The early machines used the first structure, and concurrent operation of controls was possible only by starting several controls and by very carefully programming the timing for the data transfers. Two conditions occurred to cause this: The buffering for a T or an Ms was associated with the processor, and the control could not signal the processor. Although rather trivial to implement, the idea of allowing a K to signal the processor (item 2 above) did not occur until after the idea of arithmetic processor traps was incorporated into processors. The interrupt was used as the method by which a K communicated its desire to converse with a P. The early IBM 709 provided a separate, independent processor for handling the communication with input/output equipment. Simultaneous processor-to-input/output or secondary-memory dialogues could take place (provided the devices were connected to the right processor). In most of the early computers, part of the control function (data buffering) was associated with the Pc, and thus only one device could operate at a time. This stemmed from the comparatively high cost of registers, so that links were established for a fixed period of time during a complete block transfer of data.

In some of the military computers a duplicate set of K's is provided for reliability. The more elaborate switching structures (types 3 and 4 above) are rarely used between Pio's and K's; thus to work on a peripheral requires the use of the rest of the computer. The S.dual-duplex is becoming more common; it provides a method of offline operation for maintaining better component utilization and a more reliable structure.

The switches that link a control with a particular terminal or secondary memory are generally fairly straightforward. Normally, a fixed-duplex switch is used. However, a dual-duplex switch is used if multiple access paths to the component are required. The switch links a secondary memory to a control during the transmission of relatively long, information units (e.g., records). A typical example of such a switch is the bus structure used when magnetic tape units connect to a common control. Only one of the units operates at a time (although all can be rewinding simultaneously). The switches are far less interesting than those above. Because they are nearer the periphery, failure in them does not imply a failure in the complete system.

The emergence of complex PMS structures is coincident with the development of functionally specialized processors. In the simple computers of Figs, 7 to 11 there is place only for Pc. In the general lattice there can be a Pc specialized to perform no input/output operations; one or more Pio's specialized to communicate with the