|
|
John is a Researcher in Microsoft Research's Silicon Valley lab,
which he joined in March, 2007. His widely varied research interests include computer architecture, embedded systems, application behavior and performance tuning, and hardware-software co-design and interaction.
Brief Bio
John was previously a member of Stanford's Hydra research group, which investigated a thread-level speculative Single-Chip Multiprocessor. John completed his PhD in Electrical Engineering at Stanford University at the end of 2006.
His research focused on building a Flexible Architecture for Simulation and Testing, FAST . His disseration describes the hardware and
software required to build a reconfigurable prototyping platform focused on implementing computer architectures with novel memory system designs like Hydra or other thread-level parallel architectures.
There is a brief description of FAST available on Wikipedia if reading a dissertation is not your thing.
John received his BS in Computer Science and Engineering from the University of Washington in 1997. He later spent two years as a faculty research assistant for
the Computer Science department at the University of Maryland in College Park. Simultaneoulsy, John worked on various bioinformatics projects at
Johns Hopkins Medical Institute for the Department of Pathology. John was awarded his MS in Electrical Engineering from Stanford with an emphasis in Compilers and Digital Circuit Design in 2001.
John also spent three years working in the Niagara Architecture Performance Group for Sun Microsystems from 2003-2006.
Published Papers
Conference
papers |
Martha Mercaldi Kim, John D. Davis, Mark Oskin, Todd Austin.
Polymorphic On-Chip Networks, International Symposium on Computer Architecture (ISCA-35), June 2008. (to appear)
[PDF]
John D. Davis, Zhangxi Tan, Fang Yu, Lintao Zhang.
A Practical Reconfigurable Hardware Accelerator
for Boolean Satisfiability Solvers, 45th Design Automation Conference, Anaheim, June 2008 (to appear)
[PDF]
John D. Davis, Zhangxi Tan, Fang Yu, Lintao Zhang.
Designing an Efficient Hardware Implication
Accelerator for SAT Solving, SAT , Guangzhou, P.R. China, May 2008 (to appear)
[PDF]
John D. Davis, James Laudon, and Kunle Olukotun.
Maximizing CMP Throughput with Mediocre Cores.
The Fourteenth International Conference on Parallel Architectures and Compilation
Techniques, Saint Louis, Missouri, September 19, 2005.
[PDF]
[Slides]
Lance Hammond, Vicky Wong, Mike Chen, Brian D. Carlstrom, John D. Davis, Ben Hertzberg, Manohar K. Prabhu, Honggo Wijaya, Christos
Kozyrakis, and Kunle Olukotun.
Transactional Memory Coherence and Consistency.
Proceedings of the 31st International Symposium on Computer Architecture, June 2004.
[PDF]
K. Stoffel, J. Davis, J. Saltz, G. Rottman, J. Dick, W. Merz and R. Miller.
A Graphical Tool for Ad Hoc Query Generation.
Proceedings of the 1998 AMIA Fall Symposium, Orlando, Florida, November 7-11, 1998.
[PDF]
|
Workshop
papers |
John D.Davis, Stephen E. Richardson, Charis Charitsis, and Kunle Olukotun.
A Chip Prototyping Substrate: The Flexible Architecture for Simulation and Testing (FAST).
Workshop on Design, Architecture and Simulation of Chip Multi-Processors (dasCMP 2005), Barcelona, Nov. 2005, also
appears in Computer Architecture News, Volume 33, Issue 4, November 2005.
[PDF]
John D.Davis, Cong Fu, and James Laudon.
The RASE (Rapid, Accurate Simulation Environment) for Chip Multiprocessors.
Workshop on Design, Architecture and Simulation of Chip Multi-Processors (dasCMP 2005), Barcelona, Nov. 2005, also
appears in Computer Architecture News, Volume 33, Issue 4, November 2005.
[PDF]
John D. Davis, Lance Hammond, and Kunle Olukotun.
A Flexible Architecture for Simulation and Testing (FAST) Multiprocessor Systems.
Workshop on Architecture Research using FPGA Platforms, preceding the 11th International Symposium on High-Performance Computer Architecture, Feb. 2005.
|
|
