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BEE3
Revitalizing Computer Architecture Research
The Problem:
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Computer Architecture is increasingly incremental, and
boring
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Many papers study a tiny feature, and report 5%
improvements.
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Simulation is too slow to allow
full-system experiments running real software.
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Researchers
can no longer build real chips to test new ideas – it’s too
expensive.
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Our Goal: Change this.
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Provide an experimental platform for the
research community.
The Solution: BEE3
BEE3 stands for the Berkeley Emulation Engine version 3. The BEE3 system is a 2U chassis with a tightly-couple 4 FPGA system that is a vehicle for Computer Architecture Research. In particular, the BEE3 is the target platform for the Research Accelerator for Multiple Processors (RAMP). RAMP is a collection of six universities (Berkeley, Stanford, UW, UT, CMU, and MIT) and several industry partners including: Microsoft Research, Xilinx, Sun Microsystems and IBM. The BEE3 is a scalable platform, 1 to 64 2U systems, that facilitates research in a multiple areas: Computer Architecture, Systems, OS and Software, Memory Hierarchy and Storage, and various Application/Algorithm Accelerators, to name a few. The pictures below show the rack mounted 2U BEE3 system and the inside of the 2U system with the major components labeled.
The BEE3 system is made up of a Main Printed Circuit Board (PCB) and a Control & I/O PCB with the following components: · 2U Enclosure with standard PC components o Fans, power supply, etc. · BEE3 Main PCB o 4 Xilinx FPGAs (FF1136 package) § Virtex-5 LX110T, LX155T, or SX95T o 16 DDR2 DIMMs § 2 DDR2 (400) channels per FPGA § Up to two 4 GB DIMMs per channel o FPGA Ring Interconnect o 8 10 GBase-CX4 Interfaces o 4 PCI-Express slots (endpoint only) o 4 QSH-DP (40 LVDS pairs) Connectors o 4 1GbE RJ45 Ports · BEE3 Control & I/O PCB o 4 RS232 via RJ45 Connectors o 4 SD Slots § Per FPGA Persistent Storage o 1 Compact Flash slot and System Ace support § FPGA Configuration Storage (Bit Files) o 1 Xilinx USB-JTAG Interface o 2 SMA Clock Inputs o Power Switch o Global Reset Button The BEE3 Main PCB connectivity is shown in the diagram below:
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Project Members
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