Slide 37 of 89
This is a 4 kilobits core memory plane in a 64 x 64 array. Twelve planes were stacked together as a module that had a cycle time of one microsecond and 200 nanosecond access time. 6600 had a many because you needed 5 for its 60-bit word. Ten for the PPU’s, then 32 banks of 60 bit words meant 32 times five or 4 K 170 modules in the 128 Kiloword machine.
By having 32 banks of one microsecond memory, the bandwidth was in theory 32 Million words per second or roughly 256 Mbytes/second. Now the machine could operate at roughly 3 Million floating point ops per second, this meant that the processor was unlikely to be waiting because of memory conflicts.