8 Part 1½
Fundamentals Section 1½
Abstraction and Notation
controller can fetch and execute. The central processor is interrupted only after the entire program of I/O events has been completed (exam pie: IBM System/360 and System/370 channel processors).
Position 7 The I/O processor has a local memory of its own, becoming a computer, and forms a network with the central processor (example: CDC-6600).
Position 8 The I/O processor has a general computer instruction set and may undergo an evolution of its own by being assisted by more and more sophisticated controllers (positions 1 to 7).
A study of the evolutionary chains outlined as parts of the computer space in Part 1, Sec. 2, and Part 2 will enable the reader to recognize the current evolutionary position of a particular computer system and to predict the next phase. The reader is also encouraged to identify wheels of reincarnation (evolutionary chains spiraling around themselves).
Plan of the Book
The book is divided into four parts. The introductory Part 1 is subdivided into three sections. Section 1 presents the hierarchical nature of computer structures as well as the PMS and ISP notations. Section 2 provides a cursory description of the space of computer systems. All computer systems can be viewed as occupying a space whose dimensions are the system's important features. Many features of the actual systems are locked together, as, for example, the relationship between word size and number of instructions in the repertoire: no 12-bit machine has 200 instructions, but several with 32 hits have this capacity. The number of significant variables is much less than the total number of features of computer systems. Such a space provides a basic frame in which to choose representative computer systems for inclusion in the book. Section 3 presents several historically significant computers illustrating the various computer classes. These chapters also serve to familiarize the reader with the notations and abstractions presented in Sec. 1.
Part 2 is a detailed look at eight regions of computer space. Each section in this part illustrates by examples the taxonomy and evolution of design dimensions and contains a series of papers describing computer structures in which these dimensions are prominent. This format enables the reader to focus on variations within a single dimension.
Part 3 organizes computers into classes. The rationale for classes and the properties of each class are explored. Examples of the computer structures allow the reader to observe variations in computer space dimensions for a set of comparable machines. The computers in the smaller classes are described down to the register-transfer level. Larger computers are, by necessity, abstracted to higher levels in the hierarchy. However, the details in the smaller classes should provide the reader with enough experience to extrapolate larger designs through at least the register-transfer level.
Part 4 focuses on series of computers constrained by a common ISP so that they can all execute the same code. These families provide a unique opportunity to study the impact of implementation variations, since several major computer space dimensions are held constant within the family. A simple performance model is used to predict these variations.
A word needs to be said about the "virtual" table of contents. Many of the computer structures are relevant to more than one part and section. Physically, each chapter has to be located at one place in the book. But we have made multiple entries in the Table of Contents, so that, for instance, Chap. 43, on the CDC 6600, physically appears in Part 3, Sec. 4, on maxicomputers, but also forms a significant entry in Part 2, Sec. 3, on concurrency. The book may be read according to the physical table of contents. If it is desired to treat a single topic in depth without reading the entire book, the virtual table of contents should be used as a guide.
References
Myer and Sutherland [1968].