346 Part 4 The instruction-set processor level: special-function processors

acute packaging problem. He and his co-workers have been led to consider the use of switch-core decoding [Wilkes et al., 1958a].

Eachus¹ and his co-workers have evolved yet another switch-core system which does not depend on coincident current switching.

Since the order code is only a small problem in the design of a microprogrammed machine (GOTT SEI DANKE), there is little need to dwell on it. There are several comments of design interest, however.

We were unable, with this structure, to get the multiplication below five microsteps per iteration, nor the divide below six, thus costing respectively 20 and 24 m sec per bit dealt with. Moreover, division required some precalculations (overflow detect) and some postcalculation (obtaining a rounded quotient with a correct remainder) which further boosted its time.

Because of the asynchronous nature of transfer, it is not possible to read into and out of a register simultaneously. Hence, shifting one register requires two steps, or 8 m sec per bit, and double-length shifting requires 16 m sec. This is painful.

Because of the short words, four double-length orders were microprogrammed: add, subtract, clear and add, and store. These take a total of 60 m sec to execute.

A rich collection of branch orders was included. BRanch Unconditionally, BRanch Negative, and BRanch Zero are self-explanatory. BRanch on B is the tally loop order which decreases (B) by one, and branches if it does not go negative. BR1, BR2, BR3, and BR4 are sense toggle branch; if the toggle is set, it is turned off and the program branches. These sense toggles are actually storage flip-flops T1, T2, T3, and T4 of the alteration unit. These may be set by other orders. T1 is also used as an overflow mark.