VAX-11/780: A VIRTUAL ADDRESS EXTENSION TO THE DEC PDP-11 FAMILY 411
4. The VAX/VMS file system is the same as that used on the RSX-11M/IAS operating systems, permitting interchange of files and volumes. The file access methods as implemented by the RMS record manager are also the same.
5. VAX-11 high level language compilers accept the same source languages as the equivalent PDP-l1 compilers, and execution of compiled programs gives the same results.
The coverage of all these aspects of VAX-11s well beyond the scope of any single paper. The remainder of this paper discusses the design of the VAX-11 native mode architecture and gives an overview of the VAX-11/780 system.
VAX-11 NATIVE ARCHITECTURE
Processor State
Like the PDP-11, VAX-11 is organized around a general register processor state. This organization was favored because access to operands stored in general registers is fast (because the registers are internal to the processor and register accesses do not need to pass through a memory management mechanism). Also, only a small number of bits in an instruction are needed to designate a register. Perhaps most importantly, the registers are used (as on the PDP-11) in conjunction with a large set of addressing modes which permit unusually flexible operand addressing methods.
Some consideration was given to a pure stack-based architecture. However, it was rejected because real program data suggests the superiority of two or three operand instruction formats [Myers, 1977]. Actually VAX-l1 is very stack-oriented, and although not optimally encoded for the purpose, it can easily be used as a pure stack architecture if desired.
VAX-11 has 16 32-bit general registers (denoted R0 through R15) which are used for both fixed and floating-point operands. This is in contrast to the PDP-11 which has eight 16-bit general registers and six 64-bit floating-point registers. The merged set of fixed and floating registers was preferred because programming is simplified and a more effective allocation of the registers is permitted.
Four of the registers are assigned special meaning in the VAX-11 architecture.
1. R15 is the program counter (PC) which contains the address of the next byte to be interpreted in the instruction stream.
2. R14 is the stack pointer (SP) which contains the address of the top of the processor defined stack used for procedure and interrupt linkage.
3. R13 is the frame pointer (FP). The VAX-11 procedure calling convention builds a data structure on the stack called a stack frame. FP contains the address of this structure.
4. R12 is the argument pointer (AP). The VAX-11 procedure calling convention uses a data structure called an argument list. AP contains the address of this structure.
The remaining element of the user-visible processor state (additional processor state seen mainly by privileged procedures is discussed later) is the 16-bit processor status word (PSW). The PSW contains the N, Z, V, and C condition codes which indicate, respectively, whether a previous instruction had a negative result, a zero result, a result that overflowed, or a result that produced a carry (or borrow). Also in the PSW are the IV, DV, and FU bits which enable processor trapping on integer overflow, decimal overflow, and floating underflow conditions, respectively. (The trap on conditions of "floating overflow" and "divide by zero" for any data-type is always enabled.)
Finally, the PSW contains the T bit which, when set, forces a trap at the end of each instruction. This trap is useful for program debugging and analysis purposes.