propagate control. via its "activate-next" output port: Information about the condition of the DM part (e.g., whether a certain memory location is zero) is also led back to the control part via Boolean data links (----) to affect the operation control sequence.

The data-memory portion of the system provides several functions: storing of data in memory (M) components; transmission of data to and from the outside world via transducer (T) modules, -- for example to or from analog, high voltage, low current or manual links (the links are shown as ^__ -, ^__ -); execution of data operations on various data cells via the RTM Bus \Bus, shown as heavy parallel lines (i.e., === ). Another module on the RTM Bus, the K(bus sense)\Kbus, controls the flow and timing of information and serves several other functions. While the bus is a common entity in digital systems engineering, it is not a primitive component, and the bus of the previous figure is more correctly shown in Figure 3. The RTM Bus is actually a set of 21 parallel links (wires) to which the M, DM, and T modules connect. Each module has a switch which allows it to be connected or not with the links. The actual function of each wire will be described later. For brevity, we shall normally present the Bus as in Figure 2.

In most diagrams only the K components connected by the control flow links will be given, together with the DM, M, and T components. The interconnection between the control and data-memory parts will be implied by the control part. Removing the interconnecting links, Figure 2 becomes Figure 4.

System design with the modules can best be illustrated with a simple example. Consider the algorithm for summing the positive integers from 1 to N, shown in Figure 5. Note that the computation is actually taken from N to 1, where N > 1. The diagram of an RTM system that implements this algorithm is shown in Figure 6. The design procedure for obtaining this design result from the algorithm is quite straightforward. First an appropriate set of data-memory (DM) modules from the possible set is selected, and each module is connected to the RTM Bus. For this problem, a T(switches) module allows an external environment (a human) to specify the value N, and -a DM(general purpose arithmetic unit) holds a counter, I, of the index to N, and the sum, S. The Bus requires a Kbus module attached to it, for sensing and controlling the Bus. Next the flowchart of the control algorithm is directly mapped into a network of control (K) modules. Then the wires implied by the algorithm statements and shown as dashed lines in the figure are run from the control part to the data and memory part to evoke the appropriate operations. This completes the RT level design.

The next step is the physical implementation of the system. It is usually the practice to use prewired panels, upon which the power, RTM Bus, and operation completion lines are already wired in some standard format. The only wires that have to be added to this panel are the control wires shown as solid and dashed lines in Figure 6. When the wiring has been completed, the DM, T, and K modules plug into the panel, and the panel is connected to an appropriate mounting rack, which contains the power supply.

Figure 7a gives the complete parts list for this example, plus the module locations on the mounting panel. Figure 7b shows the RTM system diagram with complete information on pin numbers for wiring. In this figure we have superimposed the block diagram notation used in this chapter on the standard DEC notation for PDP-16's. This is for the benefit of the reader who is using the PDP-16 handbook. The only other place in this book that we refer to the DEC notation is in Chapter 7. Note that Figure 7b contains the complete design documentation of the system. However, if one wishes a more systematic wiring list, one can be derived, as shown in Figure 7c. Figures 8a, b, and c show photographs of various parts of the system.