632 Appendix
2.5 The memory expression specifies the contents of a memory (an instance of a data-type) by giving the memory switch (possibly compound), as seen from PMS. However, all that is represent in ISP is the address that is used to control the switch. The address is a data-type, usually represented as a positive integer. The element-range is a field. In both cases it is possible to specify an arbitrary list of contents (addresses and fields), although in most processors this can never arise. The address-range x :y means from address x to address y inclusive.
EXAMPLES OF REGISTERS
|
A2 or A; |
boolean-memories; scalar bits |
|
sign bit/sign_ bit/sb |
|
|
1b; b2; 2C1; 2C2' ; C"; C' "; "+"; "A" |
|
|
end_ around_ shift or end around shift |
identical names |
|
G3 |
ternary memory |
|
iá 2ñ ; Zá añ |
scalar bits of an array |
|
bcá 12:8ñ or bcá 12, 11, 10, 9, 8ñ |
identical registers |
|
ACá P,Q,S,1:35ñ |
38 bit register |
|
Xá 0:7ñ 8 or Xá 0:23ñ 2 or Xá 0:23ñ |
identical registers |
|
M[0:77778]á 0:11ñ or M[0:40951á 0:3ñ 8 |
identical vectors |
|
X[0:15][0:15]á 31:0ñ |
16x16 matrix |
|
M[0:71[0:31][0:127]á 0:11ñ |
3 dimensional array |
EXAMPLES OF RESTRUCTURING AND RENAMING
Aá 17ñ : = Bá 4ñ ; Aá 0:1ñ : = Bá 0, 4ñ
opá
0:2ñ
: = i[1]á
9:11ñ
A[0:3]á
0:7ñ
= A'á
0:31ñ
indicator[11000012] = sense_ switchá Añ
XR[1:2][1:3] á
B, A, 8, 4, 2, 1ñ
: = M[87:89, vectors formed from
92:94]á
B, A, 8, 4, 2, 1ñ
single bit vector
EXAMPLES OF REGISTERS FORMED BY CONCATENATION
LACá
L, 0:11ñ
: = Lð
ACá
0:11ñ
ABá
0:47ñ
:= Aá
0:23ñ
ð
Bá
0:23ñ
EXAMPLES OF REGISTERS FORMED BY A LIST OF REGISTERS
C, Dá 0:4ñ : = Bá 7ñ , Aá 1:4ñ ð Zá 8ñ
2.6 An address-expression is an operation-expression on addresses, i.e., using only the address-operations available in the processor. An address-expression may imply the use of memory if it involves nested parentheses; such memory is assumed to be temporary with no permanent effect on the memory state.
2.7 A condition is given as a boolean, that is, as either true or false (equivalently, 1 or 0), or the result of a boolean expression involving the logical connectives or relations among data-expressions (see Table 4, ISP 3, and also GC 13). A condition can also be given as a memory-expression, in which case the memory contents are normally evaluated as a boolean vector with all 0s being false, and not all 0s being true.
2.8 Data-expressions are either instances of data-types; the contents of a memory, as given by a memory-expression; or the results of operation-expressions. which is to say, the results of operating on data-types by the data-operations available in the processor. Data-expressions may imply the use of memory if they involve nested parentheses. Such memory is assumed to be temporary, with no permanent effects on the memory state of the processor or memory. The data-type name may sometimes follow the data-expression, {data-type), in order to carry more information and avoid more complex names for memory-expressions, etc. (see Chap. 2, page 30, and ISP 3.1).
2.9 Operation-expressions are the form used by the operations (see ISP 3). Note that the operation-expression as a whole can be modified by an operation modifier enclosed in braces.
EXAMPLES OF INSTRUCTIONS
add (: = op = 101) ®
(Lð
AC¬
Lð
AC + M[z]) integer add
jms (:= op = 100) ®
(M[z] ¬
PC; next PC ¬
z + 1) jump to subroutine
FAD (:= op = + 767) ®
(FAC ¬
FAC + M[x] {s.f}) single precision floating point add
add ®
(A ¬
A + M[x] {two's complement}) the operation code need not be given
skip (:= op = 67)® ((A> 0)® P¬ P + 2;
(A=0® P¬ P+ 1)
add/ "A" (: = op = 110001)®
(0v, M[B] ¬ ; M[B] + M[A] {string})
"B"(: = op = 1)®
(A¬
M[t][s])
((A L
B) V (C > F))®
(G ¬
G + H)
3. Operations
3.1 Operations are defined to produce results of specific data-types from operands of specific data-types. The data-types themselves determine by and large the possible operations that apply to them. No attempt will be made to define the various operations here, as they are all familiar. Table 4 gives the notation for the operation-types, organized by data-types. In