ing for multiple instructions). These attributes are independent of one another and are discussed in Chap. 3.
12.1 Computer / C = simple-computer ÷ compound-computer ÷ network
12.2 simple-computer = component (
structure: 1Pc ÷ 1 Pc.interrupt;
subcomponents: Pc, Mp-set, *controlled: component-set(Pc);
function: (scientific ÷ business data processing ÷ general purpose ÷ process control / control ÷ communication : = (switching ÷ store and forward)÷ terminal control / input-output / io ÷ display ÷ file processing / file control ÷ time-sharing);
A simple computer consists of a single Pc (possibly with interrupt capability) with an Mp (possibly a set of them) plus some set of transducers, Ms's, switches, and controls. It is a complete system that can stand alone and accomplish processing for a wide variety of functions.
Almost all of its significant parameters are derived from those of the Pc or the Mp (using the Mp with the minimum cycle time if there are several Mp's).
EXAMPLESC('Whirlwind I: Mp(core; 8m s/w; 2048w; 16 b/w);
Pc(M.processor_ state: ~2w; 1 instruction/w; 1 address/ instruction); 1948 ~1966)
C('LGP-30; technology: vacuum tubes; power: 1500 watts;
Mp(drum, 4096 w; 31 b/w; t.access: .260 ~ 16.6ms);
Pc(1 address/instruction; 1 instruction/word; Mps: ~2w))
12.3 compound-computer : = simple-computer(
structure: ((1 Pc, n Pio) ÷ (1 Pc, n Pio, P.display) ÷ (2 Pc) ÷ (n Pc multiprocessor) ÷ (n Pc, P(array) ÷ (n Pc, special algorithm) ÷ (n Pc parallel processor));
subcomponents: Pc-set, Mp-set, *controlled: component-set(Pc-set))
The essential feature of compound computers is to have more than one processor. This is indicated primarily by the structure parameter but requires augmenting the subcomponents to include a set of Pc's. Other than this, compound-C's are the same as simple-C's. although some parameters (such as instruction-type) may not have simple values if several Pc's differ radically.
The simpler compound-C's retain a single Pc, but add input/output processors (Pio's and then P.display's). The next step is to limited multiprocessing, with 2 Pc's, and on to n Pc's operating on many programs, and finally to parallel processing operation on many tasks of a single program. A parallel processor is distinguished from a network; namely, there is no way to decompose a parallel processor into disjoint C's (with Pc's and Mp's). In both multiprocessing and parallel processing there may or may not be Pio's, P.display's, and other special-function processors.
EXAMPLESC(1 Pc-8 Pio; 'IBM 7094 II; Mp (32768 w; 1.4m s/w; 36 b/w);
Pc(1 address; 1 instruction / w; Mprocessor state: 12 w; data-types:(integer, word, bv, sf, suf, df, duf, fr.i); 1962 ~1966)
C(multiprocessor; 'Burroughs D-825; Mp(65 kw; 4.8m s/w; 48 b/w); 16 (Pc, Kio); Pc(stack; 12 b/syllable; 1~ 7 syllable / instruction; data-types: integer, floating, single character, boolean vector))
12.4 network/N : = dual-C ÷ network-C ÷ C-set.
A network is any collection of two (dual-C) or more computers not interconnected through primary memory. The network-C is a special case of a single physical structure which is usually called a single C but by its structure is a network (for example, CDC 6600). Finally, a set of interconnected computers that are physically separate are the most general case of networks.
Making use of the prior general conventions and the PMS definitions, ISP is developed systematically. We do this only for the processor and not for controls (though the system might be adapted to that end). Several notations are added to make ISP conform with currently existing notations.
The top-level entities of ISP-data-types, operations, the interpreter, and the instruction-set-are values of corresponding attributes in the PMS definition of a processor. An image of all the PMS structure for a computer system exists in the instruction set of the processors that control the PMS components. PMS notation is assumed for this. In ISP the primary memory (Mp) is usually named M; all other memories must be specifically declared and named.