Chapter 35 PILOT, the NBS multicomputer system 443

Addresses alpha. beta and gamma written in the instruction word are subject to automatic modification if desired by writing a 1-digit in a specified bit position. Such addresses are called relative addresses. Each of the three addresses (a , b , and g ) in each instruction word contains a 4-bit code group, called the a-, b-, and c-digits respectively, in which any base register identification number (0 through 15) may be written. When this is done, the address number to which the computer actually refers is equal to the sum (modulo 2¹⁶) of the address number stored in the designated base register plus an address-modification constant, indicated in the remaining 12 bits of the 16-bit address segment of the instruction word.

Fast access memory. Because of budget limitations, the initial installation of the system will contain only a relatively small section of internal memory of the diode-capacitor type. This diode-capacitor memory, originally developed at NBS in 1953, is very fast; i.e., capable of providing one random access per micro second, but it has the disadvantage of relatively high cost per word of storage. This type of memory is available in modules of 256 words subdivided as follows:

The over-all system is designed to accommodate up to 32,768 internally-accessible full-words, which may be held in storage units with access times ranging from 1 microsecond (m sec) to 32 m sec. Thus the minimum fast access memory can be backed up with a much larger and slower magnetic-core memory.

Inter-memory transfer trunk. Provision is made for transferring blocks of information between the various internal storage units in the system, concurrently with computation. The size of the block transferred may range from a single word to the entire contents of the memory, and the addresses between which the information is transferred are specified by a single programmed inter-memory transfer instruction. Automatic interlocks are provided to insure that all future references which the program may make to any memory positions involved in the inter-memory transfer operation are automatically made after the data have been shifted to the new locations.

Arithmetic and processing unit. The secondary computer is a high-speed independently programmable general-purpose computer that operates in conjunction with the primary computer and can perform 16 distinct types of operations using 16-bit words. These operations include 6 arithmetic-processing operations, 4 choice operations, 1 nonnumerical processing operation, and 5 operations that transfer digital information or control-signals between the primary and the secondary computers. See Table 2. Operation times for the secondary computer average about 2 m sec.

Both computers operate concurrently and can transfer information back and forth between each other. One of the principal functions of the secondary computer is to carry out so-called "red-tape" operations, such as: (1) counting iterations, (2) systematically modifying the addresses of the operands and instructions referred to by the primary program, (3) monitoring the primary program, and (4) various special tasks. Through the use of special subroutines for the secondary computer, both computers acting co-operatively can be made to carry out a wide variety of complex operations without unduly complicating the writing of the primary computer programs. Examples of such operations are: (1) special types of sorting, (2) logarithmic search, (3) routines involving cross-referencing, or items selected according to an attached code, (4) error analyses, and (5) operations involving small numerical fields.