Section 2 Computers with one central processor and multiple input/output processors 397
tion Laboratory at Livermore, the Control Data 6600 (Chap. 39), and the IBM System/360, Models 91 and 85.
Stretch derives its power through:
1 Compound and complex ISP instructions
2 A PMS structure with Mp(2.18 m s/w),Pc(0.25 ~ 1 m s/w), Pio's, and a satisfactory switch between P's and Mp
3 Many data-types
4 Parallelism within the Pc, involving concurrent interpretation of the instruction stream using the "Instruction look-ahead" mechanism
The last of these, internal Pc parallelism, is the most novel. Stretch was possibly the earliest computer to make use of it; each of the other "maximum" power C's listed above also uses some version of instruction look-ahead, for each of these "maximum" systems is faced with how to obtain computing power that goes beyond the basic logic and memory technology available at the time the system is designed. The conclusion, reached in all these cases, is to move toward internal parallelism.
In Stretch the instruction look-ahead mechanism fetches the next several instructions and partially interprets each future instruction. The mechanism is elaborate compared with the straightforward instruction stack in the CDC 6600 (Chap. 39, page 489). The Stretch look-ahead complexity stems from partially interpreting instructions which may later have to be undone.
Stretch uses a basic Mp(core; 16384 w; (64 + 8 parity) b/w; tc:2.18 m s). Sixteen Mp's can be connected to the P's via the S('Memory Bus; time multiplexed). The 8 parity bits are used to give single-error correction and double-error detection, which is a very substantial amount of error protection compared with standard design practice. This is the memory that was incorporated in the IBM 7090 and became operational even before Stretch was delivered. Thus, as is often the case with large development efforts, the by-products are as important as the main product.
There is a single well-designed physical Pio, called the Exchange, consisting of several logical Pio's. Its ability to have the state of all the logical Pio's accessible in Mp is useful and important. This design seems better than the data channels in the IBM 709-7094 series. It is almost a prototype for the IBM System/360 Pio's.
The Stretch word length is 64 bits. It has operations on the following data-types: binary integers, decimal integers, address integers, variable-length integers, boolean vectors, single and double floating point. The length of the variable integer is specified by parameters in the instruction. Noisy-mode floating-point data provide a method of introducing a roundoff error in the least significant bit under program control. Thus a problem can be run in conventional and noisy modes and the results compared. An instruction is either 32 or 64 bits.
The ISP processor state has an instruction counter, a double-length accumulator, 15 index registers, about 6 registers, and about 100 miscellaneous bits. Computing power is obtained by having an instruction set with complex instructions. Hence, there is an instruction for almost every possible operation, though inverse subtract and inverse divide instructions are lacking. However, there is a "multiply and add" instruction. Stretch has the complete set of 16 operators for boolean vectors. Compound instructions, formed from a sequence of simpler instructions, also increase power. These instructions specify the array element to be accessed, an operation on the element, and a calculation to get the next element, in a single instruction. Notice that several of these instructions are oriented toward operations on arrays (i.e., matrices), which are the type of numerical-analysis tasks for which the system was built.
Multiprogramming was done with Stretch [Codd et al., 1959] and undoubtedly had some influence within IBM. Stretch has a pair of bounds registers to relocate and protect a single program. The interrupt scheme for Stretch [Brooks, 1957a] was better than that of existing IBM computers, though it is not described in Chap. 34.
The importance of Stretch lies in the by-products it inspired and its influence on IBM, encouraging a concern with hardware project management. The elaborate ISP and the complex implementation of Stretch may not have been worth the effort, especially when one compares this computer with the later, larger but elegant CDC 6600. It is, however, interesting to note that Stretch was used as a central component in an early specialized multiprocessor system called the IBM Harvest [Herwitz and Pomerene, 1960], which provides extremely powerful data-processing capabilities.
PILOT, the NBS multicomputer system
The National Bureau of Standards' PILOT computer (Chap. 35) was first described in 1959. At that time it was a multiple computer; by our criteria, we classify it as a multiple-processor computer, as shown by its PMS structure (Fig. 1). However,