292 Part 3 The instruction-set processor level: variations in the processor
Section 6 Processors with multiprogramming ability
Fig. 1. Configuration of equipment.
1 If a hardware interrupt occurs
2 If a trap is generated by the user program as outlined.
3 If an instruction with a particular configuration of two bits is executed. Such an instruction is called a system programmed operator (SYSPOP).
In case 3, the six-bit operation field is used to select one of 64 locations in absolute core. The current address of the instruction is put into absolute location zero as a subroutine link, the indirect address bit of this link word is set, and another bit is set, marking the memory location in the link word as having come from user-mapped memory. The system routine thus invoked may take a parameter from the word addressed by the SYSPOP, since its address field is not interpreted by the hardware. The routine will address the parameter indirectly through location zero and, because of the bit marking the contents of location zero as having come from user mode, the user map will be applied to the remainder of the address indirection. All calls on the system which are not inadvertent are made in this way.
A monitor mode program gets into user mode by transferring to an address with mapping specified. This means, among other things, that a SYSPOP can return to the user program simply by branching indirect through location zero.
As the above discussion has perhaps indicated, the mode-changing arrangements are very clean and permit rapid and natural transfers of control between user and system programs. Advantage has been taken of this fact to create a rather grandiose machine for the user. Its features are the subject of this paper.
Basic features of the machine
A user in the Berkeley time-sharing system, working at what he thinks of as the hardware language level, has at his disposal a machine with a configuration and capability which can be conveniently controlled by the execution of machine instruction sequences. Its simplest configuration is very similar to that of a
Fig. 2. The hardware memory map. (a) Relation between virtual and real memory for a typical map. (b) Construction of a real memory address.