Section 5 Processors with stack memories (zero addresses per instruction) 261
d2¬ u d1
d3 ¬ d1 b d2
In either of these cases d1 d2, or d3 can be the top of Stack/S; or Mp[Address + Base Address + [å index registers [ABC]]]. This flexibility allows the Pc to behave as a 0,1, 2, or 3 address per instruction processor.
The B 5000 is more conventional than the D825 in its use of stacks (see references, Table 1). There are only load and store (that is, push and pop instructions) to transfer data between Mp and one stack. Actually, the B 5000 has several important features that make it worthy of study:
1 The stacks.
2 Data-type specification. A data type is declared by placing a type identifier with the data. Thus, for example, there is one add operation for both fixed and floating point, the data telling which addition is to take place.
3 Multiprogram mapping. Descriptors are used to access variables (scalars, vectors, and arrays). This indirect addressing technique allows multiprogramming; how ever. the reader should note that the data are not protected against other accesses (corrected in the B 6500).
4 Failure of the Pc.stack for character processing. The B 5000 has a character mode to allow processing of string data, and the stack is not used in this mode. In effect, a separate string processing ISP is incorporated in the Pc.
5 Multiprocessing. A B 5000 can have two Pc's.
A command structure for complex information processing
The IPL-VI (Chap. 30) is discussed in Part 4, Sec. 4 page 348 as a language-based processor.
Microprogrammed implementation of EULER on IBM System/360
EULER (Chap. 32) is discussed in Part 4, Sec. 4 page 348 as a microprogrammed, language-based processor.