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222 Part 3 The instruction-set processor level: variations in the processor

Section 2 Processors constrained by a cyclic, primary memory

a 10-digit multiplier to develop a 20-digit product. The multiplier must be placed in the upper accumulator prior to multiplication. The location of the multiplicand is specified by the D address of the instruction, The product is developed in the accumulator beginning in the low-order position of the lower half of the accumulator and extending to the left into the upper half of the accumulator as required.

14 DIV (Divide). This operation code causes the machine to divide without resetting the remainder. A 20-digit dividend may be divided by a 10-digit divisor to produce a 10-digit quotient. In order to remain within these limits, the absolute value of the divisor must be greater than the absolute value of that portion of the dividend that is in the upper half of the accumulator. The entire dividend is placed in the 20-position accumulator. The location of the divisor is specified by the D address of the divide instruction.

64 DIV RU (Divide and Reset Upper). This operation code causes the machine to divide as explained under operation code 14 (DIV). However, the upper half of the accumulator containing the remainder with its sign is reset to zeros.

Branching instructions (decision operations)

44 BRNZU (Branch on Non-Zero in Upper). This operation code causes the contents of the upper half of the accumulator to be examined for zero. If the contents of the upper half of the accumulator is nonzero, the location of the next instruction to be executed is specified by the D address. If the contents of the upper half of the accumulator is zero, the location of the next instruction to be executed is specified by the I address. The sign of the accumulator is ignored.

45 BRNZ (Branch on Non-Zero). This operation code causes the contents of the entire accumulator to be examined for zero. If the contents of the accumulator is nonzero, the location of the next instruction to be executed is specified by the D address. If the contents of the accumulator is zero, the location of the next instruction to be executed is specified by the I address. The sign of the accumulator is ignored.

46 BRMIN (Branch on Minus). This operation code causes the sign of the accumulator to be examined for minus. If the sign of the accumulator is minus, the location of the next instruction to be executed is specified by the D address. If the sign of the accumulator is positive, the location of the next instruction to be executed is specified by the I address. The contents of the accumulator are ignored.

47 BROV (Branch on Overflow). This operation code causes the overflow circuit to be examined to see whether it has been set. If the overflow circuit is set, the location of the next instruction to be executed is specified by the D address. If the overflow circuit is not set, the location of the next instruction to be executed is specified by the I address.

90-99 BRD 1-10 (Branch on 8 in Distributor Position 1-10). This operation code examines a particular digit position in the distributor for the presence of an 8 or 9. Codes 91-99 test positions 1-9, respectively, of the test word; code 90 tests position 10. If an 8 is present, the location of the next instruction to be executed is specified by the D address. If a 9 is present, the location of the next instruction to be executed is specified by the I address. The presence of other than an 8 or 9 will stop the machine.

Shift instructions

30 SRT (Shift Right). This operation code causes the contents of the entire accumulator to be shifted right the number of places specified by the units digit of the D address of the shift instruction. A maximum shift of nine positions is possible. A data address with units digit of zero will result in no shift. All numbers shifted off the right end of the accumulator are lost.

31 SRD (Shift Round). This operation causes the contents of the entire accumulator to be shifted right the number of places specified by the units digit of the D address of the instruction. A 5 is added (-5 if the accumulator is negative) in the twenty-first (blind) position of the amount in the accumulator. A data address units digit of zero will shift 10 places right with rounding.

35 SLT (Shift Left). This operation code causes the contents of the entire accumulator to be shifted left the number of places specified by the units digit of the D address of the instruction. A maximum shift of nine positions is possible. A data address with a units digit of zero will result in no shift. All numbers shifted off the left end of the accumulator are lost. However, the overflow circuit will not be turned on.

36 SCT (Shift Left and Count). This operation code causes (1) the contents of the entire accumulator to be shifted to the left until a nonzero digit is in the most significant place, (2) a count of the number of places shifted to be inserted in the two low-order positions of the accumulator. This instruction is to aid fixed-point scaling.

Table look-up instructions

84 TLU (Table Look-up). This operation code performs an automatic table look-up using the D address as the location of

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