202 Part 3 The instruction-set processor level: variations in the processor
Section 1 Processors with greater than 1 address per instruction
C : Clear the accumulator specified by B after storing, or before addition. (In a serial machine like ZEBRA this is automatically the case, cf. Fig. 3.)
I : Subtract instead of add.
Q : Add one (unit in the least significant place) to the B-accumulator.
L : Shift both accumulators one place to the left.
R : Shift both accumulators one place to the right. The accumulators are always coupled together in shifting except when C is present.
A few more examples will be given.
A200BCE25 |
Store á Bñ in 5, clear B and add á 200ñ to B. |
X200QLIBCE6 |
Jump to 200. Store á Bñ in 6, put -1 in B (because of QIBC) and shift the A accumulator one place to the left. Shifting from B into A is prevented by the presence of C. |
X200RBC3 |
Jump to 200. Shift A to the right. Copy á 3ñ into B. As register 3 is just an address for the B accumulator itself, this means that A is shifted while B is static. |
X200K3QIBC |
Take the instruction from 200 and modify it with the contents of the B accumulator (= register 3). Put -1 in B afterwards. |
Fig. 3. Accumulator.
As can be seen, many complicated operations can be composed by the elementary possibilities of the separate bits.
The accumulator
A simplified block diagram of one of the accumulators is shown in Fig. 3.
Shifting is effected by looping the accumulator over one place less or one place more. In a double addition the contents of the drum store and the fast store are first added together in the preadder (possibly augmented by unity in the B accumulator, if Q is present) and this result is added into the accumulator (or subtracted in case of I). A clearing date controlled by C interrupts the recirculation of the previous contents.
The control unit
The control unit has two shifting registers, the C-register which receives the next instruction to be executed and the D-register or counter. The block diagram is shown in Fig. 4. After a new instruction has come into C, it is taken over in parallel form into E in the interword time. It remains in E while the next instruction is coming into C. Let us explain the action of this control with a short programme.
Examples of programmes
100 X101E5
101 AC102
102 constant
103 etc.
The actions in the several registers are now: