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196 Part 3 The instruction-set processor level: variations in the processor

Section 1 Processors with greater than 1 address per instruction


8n- 16 (transfer nth word of DL8 to TS16)
8m-n -17 (add all the words from 8m to 8n i.e. n-m + 1 consecutive words of DL8m to TS16)

Detailed coding

In the second stage of the coding the true instruction words are derived from the preliminary coding. This is a fairly automatic process and recent experience has shown that it can be carried out satisfactorily by quite junior staff. The timing of each instruction is given relative to the position of that instruction in the store. This is an incidental feature of the code which arose from the attempts to minimize equipment. It would be dropped in any future machine in favour of an absolute timing system. If an instruction occupies position m in a DL and has a wait number W and timing number T then the transfer always begins in minor cycle (m + W + 2) and the next instruction is always in minor cycle (m + T + 2) of the selected next instruction source. The period of transfer depends on the value of the characteristic. If the characteristic is zero then the transfer lasts for the whole period from (m + W + 2) to (m + T + 2), that is (T - W + 1) minor cycles. If the characteristic is one, then the transfer is for one minor cycle, that is minor cycle (m + W + 2). If the characteristic is three then the transfer is for two minor cycles (m + W + 2) and (m + W + 3). The characteristic value, two, is not used. The characteristic value zero gives a prolonged transfer which is peculiar to the Pilot ACE. The characteristics 1 and 3 are analogous to the facility on EDSAC whereby full length or 1/2-length words may be transferred. On the Pilot ACE we transfer single or double length words. This facility is invaluable for double length, floating and complex arithmetic. In the above definitions the numbers (m + W + 2) etc. are to be interpreted modulo 32. In general, timing and wait numbers are simpler than they appear from the definitions because they are very frequently both zero, corresponding to a transfer for one minor cycle. The detailed coding of the problem given earlier will illustrate the procedure. All the instructions are in DL1 so that the next instruction source is always one. The key to the headings in the following table is:

m.c.

Minor cycle position of instructions in DL1

NIS.

Next instruction source

S

Source

D

Destination

C

Characteristic

W

Wait number

T

Timing number

The last column gives the position of the next instruction in DL1; it is given by (m + T + 2). The first 4 instructions occupy minor cycles, 0, 2 and 4, 6 and each takes two minor cycles, and gives a transfer for one minor cycle only. The next instruction occupies minor cycle number S and it requires a transfer lasting 3 minor cycles. The simplest and fastest way of getting this is to have W = 0 and T = 2 giving a transfer of (2 - 0 + 1) minor cycles. The next instruction is in position (8 + 2 + 2), that is minor cycle 12, and so on. When we reach the instruction in minor cycle 31, viz. 25-17, a transfer for one minor cycle is required. The simplest way is to have W = 0 T = 0 and this makes the next instruction occupy position (31 + 0 + 2) i.e. position 33 which is position 1. If position 1 had been already occupied, a value of T could have been chosen in order to land in an unoccupied position. In order to ensure that a transfer of one minor cycle only took place, the characteristic could have been made 1. It should be appreciated that the choice of C, W and T is far from unique. Whenever possible T = 0 and W = 0 are chosen because this gives the highest speed of operation besides being simplest. The instruction occupying position 1 is of special interest because this is the last instruction of the cycle needed to build up a square and cube and it must select as its next instruction the first of the cycle, which is, in position number 6. This is achieved by making T = 3 (giving the next instruction in m.c. 1 + 3 + 2 = 6). This incidentally gives a transfer lasting four minor cycles but since it is a transfer from one TS to another and no functional source or destination is in use, the prolonged transfer produces no harmful effect. If a prolonged transfer had to be avoided then the characteristic could be taken as 1. It is seldom necessary to use any characteristic other than zero for transfers to and from TS's but when transfers are made to and from DL's, characteristic values of 1 or 3 are almost universal. All 12 instructions which comprise the repeated cycle of the computation take a total time of one major cycle exactly (32 minor cycles) the last instruction of the cycle having been specially designed to get back to the beginning of the cycle. This is in contrast to the position in a machine not using optimum coding, where 12 major cycles would be necessary quite apart from the fact that the multiplications by factors of 3 and 2, each of which uses one instruction, would normally need more than one instruction if a prolonged transfer were not available. Figure 1 gives a simplified diagram of the machine. The sequence of events in obeying the instruction

N

S

 

D

C

W

T

2

16

-

2C

0

8

10

occupying DL12 for example is as follows. Starting from the time when the last instruction was completed, the instruction from

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