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192 Part 3 The instruction-set processor level: variations in the processor

Section 1 Processors with greater than 1 address per instruction

coded. The LGP-30 (Chap. 16), by contrast, has only a basic instruction set. Hence a problem can be coded only one or two ways. ZEBRA's performance of 60 percent memory-cycle utilization is rather outstanding and raises the possibility that random-access primary memories may not be necessary.

UNIVAC scientific (1103A) instruction logic

The UNIVAC 1103A (Chap. 13) is a two-address computer. The computer was designed initially by Engineering Research Associates (ERA) of St. Paul.1 UNIVAC acquired ERA in 1952 as a scientific-computer division. The evolution of the 1103A later yielded the 1107 and 1108 general register processors. The reader should compare the 1103A with the IBM 704 series (Chap. 41). At the time both were used, it was not clear which computer was better.

The RW-400: a new polymorphic data system

The RW-400 in Chap. 38 is a two-address, binary computer. It is discussed in Part 5, Sec. 4, page 470.

Instruction logic of the MIDAC
The University of Michigan's MIDAC (Michigan Digital Automatic Computer) is based on the National Bureau of Standards' SEAC (Standards' Electronic Automatic Computer). MIDAC, a three-address, binary computer, is presented in Chap. 14.

Instruction logic of the Soviet Strela (Arrow)

The Russian Strela is presented in Chap. 15. Since it is used only to illustrate a three-address organization, the chapter consists of only the instruction set.

1As the third in a series that started with the ERA 1101 and 1102.

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