172 Part 2÷ The instruction-set processor: main-line computers
Section 2 Processors with a general register state
laid on flexibility of use and ability to work without error in high electrical interference fields. These circuits form the basis of those in Pegasus.
Operations to be carried out. The following well-known operations are used to build up the logical structure of the computer:
a 'And.' This operation, which may be carried out between two or more input serial trains of pulses, produces an output train in which pulses occur only when pulses are present at the same time on all inputs.
b 'Or.' This operation produces an output train in which pulses occur at all times when a pulse is present on any of a number of inputs.
c 'Not.' l's are changed into 0's and 0's into l's; this is achieved by inverting the pulse train.
d Digit Delay. The passing of a pulse train through a digit delay produces a pulse train similar to the input, but each pulse is one pulse position later in timing and restandardized in shape.
All operations in the computer, including addition, subtraction, and staticizing, are carried out by combinations of these elements. There is no circuit specifically for addition, and there are, in general, no flip-flops such as are often used for staticizing or storing a single digit. A similar philosophy was arrived at independently by the designers of SEAC and DYSEAC [Elbourne and Witt, 1953], but the detailed working out is considerably different.
Digit waveforms. The timing of digit pulses throughout the machine is controlled by a common 'clock' waveform-a 3 micro- sec square wave (Fig. 1a) in which the positive-going portions define digit positions.
The digit pulses, which are routed about the machine and applied to logical circuits, are generally of the form shown in Fig. 1b; as generated, they have their leading edges well in advance of the clock pulse and are of a greater amplitude. This means that considerable distortion of the pulse is tolerable, since only the portion which coincides with positive clock pulse is of consequence. Digit pulse trains are 'clocked' ('and' operation with clock) only at their entry into a storage system or into a digit-delay circuit.
Inverted pulses are also employed: as an illustration, consider the operation 'A and not B'. Pulses A and B (Fig. 1) are on two lines and are of the same nominal timing, and we wish to form A - B (symbolic representation of 'A and not B'). To do this pulse B is inverted (forming B, or 'not B') and is used to gate pulse A and prevent its passage. The inverted pulse B will be a little late on B, which also may have been later than A, as shown in Fig. 1c; thus when A and B are 'anded' together a spike may be produced, as shown in Fig. 1e. This spike, however, lies between clock pulses and so will be rejected on clocking.
The pulse system used allows several logical operations to be performed in cascade without any loss in nominal timing, so easing the problem of logical design (particularly by permitting afterthoughts). The maximum number of logical operations performed
Fig. 1. Basic waveforms.