Chapter 7 Some aspects of the logical design of a control computer: a case study 147
Fig. 1. AGC block diagram.
The only logical difference between the two memories is the inability to change the contents of the fixed part by program steps.
Each word in memory is 16 bits long (15 data bits and an odd parity bit). Data words are stored as signed 14 bit words using a one's complement convention. Instruction words consist of 3 order code bits and 12 address code bits.
The contents of the address register S uniquely determine the address of the memory word only if the address lies between octal 0000 and octal 5777, inclusive. If the address lies between octal 6000 and octal 7777, inclusive, the address in S is modified by the contents of the memory bank register MB. The modification consists in adding some integral multiplies of octal 2000 to the address in S before it is interpreted by the decoding circuitry. The memory bank register MB is itself addressable; its address, however, is not modified by its own contents.
Transfers in and out of memory are made by way of a memory local register C. For certain specific addresses, the word being transferred into C is not sent directly, but is modified by a special gating network. The transformations on the word sent to G are right shift, left shift, right cycle, and left cycle.
The middle part of Fig. 1 shows the central section in block form. It consists of the address register S and the memory bank register MB both of which were mentioned above. There is also a block of addressable registers called "central and special registers," which will be discussed later, an arithmetic unit, and an instruction decoder register SQ.
The arithmetic unit has a parity generating register and an adder. These two registers are not explicitly addressable.
The SQ register bears the same relation to instructions as the S register bears to memory locations; neither S nor SQ are explicitly addressable.
The central and special registers are A, Q, Z, LP, and a set of input and output registers. Their properties are shown in Table 1.
The sequence generator provides the basic memory timing, the sequences of control pulses (microprograms) which constitute an instruction, the priority interrupt circuitry, and a number of scaling networks which provide various pulse frequencies used by the computer and the rest of the navigation system.
Instructions are arranged so as to last an integral number of memory cycles. The list of 11 instructions is treated in detail in Sec. 6. In addition to these there are a number of "involuntary" sequences, not under normal program control, which may break into the normal sequence of instructions; these are triggered either by external events, or by certain overflows within the AGC, and