Processors with one address per instruction
This section is principally concerned with the ISP. It is the largest section in the book, reflecting the dominance of the one-address organization during the first two generations. Machines with index registers are included, but not machines with general registers, which are discussed in Sec. 2. Some processors store two single-address instructions per word, following the pattern of the IAS1 (von Neumann) machine (Chap. 4). In machines with short word lengths, one single-address instruction is stored in one or two words, for example, in the 16-bit IBM 1800 (Chap. 33) and in the 12-bit PDP-8 (Chap. 5). The evolution of these machines can be seen by comparing first- and third-generation machines (e.g., Whirlwind and the IBM 1800). In general, the section is arranged by increasing word length, alternatively complexity and performance.
Preliminary discussion of the logical design of an electronic computing instrument
This article (Chap. 4) is important for historical as well as technical reasons. It is one of a series2 written in 1946 prior to building the first fully stored-program computer. Although its authors were not engineers, it is written with the caution of those responsible for the implementation of a rather significant development task. The major problems for the computer are identified, the alternatives analyzed, and a rationale for each decision is given. If computer designers were all required to analyze and describe their machines in such a fashion prior to building them, there would be fewer, but better, computers. Some of the especially enjoyable aspects of the discussion include:
1 Selection of word length and number base.
2 Discussion of the instructions needed.
3 Concern for the input/output structure and the idea of displays (now almost a reality).
4 Rationale for not including floating-point arithmetic (caution about the technology).
5 The lack of necessity for the rather trivial binary-decimal conversion hardware and the idea of cost effectiveness.
6 Analysis of the addition, multiplication, and division hardware implementation. (This description includes a nice, one-page discussion of the average carry length for addition.)
It is difficult to say which machines have been influenced by this memorandum since the idea of data and instructions stored together in a homogeneous primary memory is so basic to all computers. The idea of the single-address instruction set and format is at the heart of all the machines discussed in this section. However, it did not have index registers. Many of the machines with long word length, like IAS, use the two-instructions-per-word format.
Subsequent machines built with only minor variations include ORDVAC; ILLIAC I at the University of Illinois with a 40-bit electrostatic memory and vacuum-tube logic; AVIDAC, ORACLE, MANIAC I, WEIZAC, SILLIAC, BESK, DASK, CSIRAC, and JOHNNIAC at the RAND Corporation with a 40-bit core memory and transistor logic [Gruenberger, 1968]. Other similar computers include the IBM 701 with a 36-bit word, electrostatic memory and vacuum-tube logic; and the CDC 1604, with a 48-bit word, core memory, and transistor logic (possibly influenced by MANIAC II).
The DEC PDP-8
The PDP-8 is included as Chap. 5 to illustrate the effects of a 12-bit word length. It is given in detail using a "top-down" approach in order that the student may thoroughly understand it by simulating it, interpreting it, writing microprograms that
1Institute for Advanced Study, Princeton University, Princeton, N.J.