Chapter 39½ Implementation and Performance Evaluation of the PDP-11 Family 667
sections summarize the major architectural features of the PDP-11, including memory organization, processor state, addressing modes, instruction set, and Unibus protocol. The references list a number of processor handbooks and other documents which provide a more precise definition of the PDP-11 architecture than is possible here.
2.1 Memory and Processor State
The central processor contains the control logic and data paths for instruction fetching and execution. Processor instructions act upon operands located either in memory or in one of eight general registers. These operands may be either 8-bit bytes or 16-bit words.
Memory is byte- or word-addressable. Word addresses must be even. If N is a word address, then N is the byte address of the low-order byte of the word and N + 1 is the byte address of the high-order byte of the word. The control and data registers of peripheral devices are also accessed through the memory address space, and the top 4 kilowords of the space are reserved for this purpose.
The general registers are 16 bits in length and are referred to as R0 through R7. R6 is used as the system stack pointer (SP) to maintain a push-down list in memory upon which subroutine and
interrupt linkages are kept. R7 is the program counter (PC) and always points to the next instruction to be fetched from memory. With minor exceptions (noted below) the SP and PC are accessible in exactly the same manner as any of the other general registers (R0 through R5).
Data-manipulation instructions fall into two categories: arithmetic instructions (which interpret their operands as 2's complement integers) and logic instructions (which interpret their operands as bit vectors). A set of condition code flags is maintained by the processor and is updated according to the sign and presence of carry/overflow from the result of any data manipulation instruction. The condition codes, processor interrupt priority, and a flag enabling program execution tracing are contained in a processor status word (PS), which is accessible as a word in the memory addressing space.
2.2 Addressing Modes and Instruction Set
The PDP-11 instruction set allows source and destination operands to be referenced via eight different addressing modes. An operand reference consists of a field specifying which of the eight modes is to be used and a second field specifying which of the eight general registers is to be used. The addressing modes are:
Mode 1 Register deferred. The contents of the specified register are used to address the memory location containing the operand.
Mode 2 Autoincrement. The contents of the specified register are used to address the memory location containing the operand, and the register is then incremented.
Mode 3 Autoincrement deferred The contents of the specified register address a word in memory containing the address of the operand in memory. The specified register is incremented after the reference.
Mode 4 Autodecrement. The contents of the specified register are first decremented and then used to address the memory location containing the operand.
Mode 5 Autodecrement deferred The contents of the specified register are first decremented and then used to address a word in memory containing the address of the operand in memory.
Mode 6 Indexed The word following the instruction is fetched and added to the contents of the specified general register to form the address of the memory location containing the operand.
Mode 7 Indexed deferred The word following the instruction is fetched and added to the contents of the specified general register to form the address of a word in memory containing the address of the operand in memory.