Chapter 34 ½ TMS1000/1200: Chip Architecture and Operation 589
state lasts for only one subsequent instruction cycle (which could be during a branch or call); then the status logic will normally revert back to its ONE state (unless the following instruction resets it to ZERO).
Like branch instructions, call instructions are conditional. One level of subroutine is permitted, and a call within a call does not execute properly. In the case of a successful call when status logic equals ONE:
1 The call latch (CL) is set to ONE.
2 The contents of the page buffer register (PB) and the page address (PA) register are exchanged simultaneously.
3 The return address is stored in SR and PB. The SR address is one address ahead of the program counter when the call instruction is executed. The return address is saved for a future return instruction.
4 The branch address field of the instruction word writes into the program counter.
When a return instruction occurs:
1 The subroutine return register (containing the call instruction address plus one) is always transferred to the program counter.
2 The contents of the page buffer register (containing the page at call) is always transferred to the page address register.
3 The call mode is reset (CL = 0).
If a call instruction is executed within a previous call (no return has occurred and the call latch is still a ONE and status is a ONE), there is no transfer of the page buffer register to the page address register; instead contents of the page address register transfer to the page buffer register, although the branch address (W) loads into the program counter.
Thus a call within a call to another page will cause the return page to change, losing the correct return page address.
An X and Y address selects one four-bit RAM character, M(X,Y), this address being the storage location in the RAM matrix. The X-register can be set to a constant equal to 0 through 3 (LDX instruction), or X can be complemented (COMX instruction) to flip the address of X to the X file (e.g., 00 to 11, or 01 to 10).
The Y-register has three purposes.
1 The Y-register addresses the RAM in conjunction with the X-register for RAM character select.
2 The Y-register is a working register. The Y-register may be set to any constant between 0 and 15 (by the TCY instruction), loaded from memory (TMY instruction), loaded from the accumulator (TAY instruction), decremented (DYN), and incremented (IYC). Note that in the functional block diagram (Fig. 1), the Y-register has no inverted adder input. Thus, the Y-register cannot be subtracted from the accumulator or memory.
3 The Y-register addresses the R-output register for setting and resetting individual latches. Whenever a particular R-output needs to be set, the constant bus inputs the R's address (0 through 12) to Y (TCY instruction), and then a set R-output (SETR) instruction is executed.
The TMS 1000 has two outputs:
The purpose of the R-outputs is to control the following:
Each R-output has a latch that stores a ONE or ZERO, and each latch may be set (ONE) or reset (ZERO) individually by the set R (SETR) or reset R (RSTR) instruction. The Y-register points to which R-output is set by these instructions.
The R-output can be strobed by the ROM program to scan a key matrix (K-input). Figure 2 represents the maximum key matrix possible without external logic. A simple short from an R line to a K-input can be detected by the ROM program and interpreted as any function or data entry. Expanding the matrix is possible by external logic such as using a 4-line to 16-line decoder.
The status latch and the accumulator data are loaded into the 0-output register (bottom right of Fig. 1) by a fixed instruction from the ROM (TDO) when the programmer decides to change output data. A separate instruction clears the O-output register. This instruction (CLO) causes all five output register bits to be reset to ZERO. The five bits from the 0 register are converted to a parallel eight-bit code by the O PLA.
The accumulator is a four-bit register that interacts with the adder, the RAM, and the output registers. The accumulator is the main working register for addition and subtraction. It is the only register which is inverted before its contents are sent to the adder for subtraction. Subtraction is accomplished by two's complement arithmetic. It is a storage register for inputs from the constant and K-input logic as well as the Y-register.
Variable data from the K-inputs is also stored via the accumula-