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The TMS1000/1200 functional block diagram (Fig. 1) shows all major logic blocks and major data paths in the TMS1000/1200 architecture. The ROM, ROM addressing, and instruction decode are on the left side of the diagram. On the right side of the diagram are the adder/comparator, the RAM, the registers for addressing the RAM, and the accumulator, which is the main working register. The major logic blocks are interconnected to the adder with four-bit parallel data paths. The various portions of the architecture will be discussed in the following paragraphs.

The ROM has 8,192 possible matrix points (1,024 eight-bit words) where MOS transistors are placed to define the bit patterns of the machine language code. The ROM is organized into 16 pages of 64 words.

There are four RAM files, each containing 16 four-bit words in the RAM's 256-bit matrix (shown in the upper right of Fig. 1).

There are two modes of RAM access (read and write) during the instruction cycle:

Two sources of information are written into the RAM; these sources are selected by the write multiplexer (shown on the right side of the function diagram, Fig. 1). In one mode the multiplexer selects the accumulator information to be written into the RAM (uses the STO microinstruction). The accumulator data is transferred to memory after data is read from the RAM but before the ALU results are stored into the accumulator. In the second mode, the constant and K-input logic is written into the RAM (by the CKM microinstruction). The constants from the ROM instruction bus are transferred to the RAM directly, and an optional data path from K1, K2, K4, and K8 exists although not selected in the standard instruction set. Four RAM bits are carried on the read bus to either the P-multiplexer or the N-multiplexer and then to the adder/comparator.

On powerup, the program counter is reset to location zero, and the PA is set to 15. Then the program counter counts to the next ROM address in a pseudorandom sequence. The sequence of addresses in the program counter can be altered by a branch instruction or a call instruction. A new branch address (W) can be stored into the program counter upon the completion of a successful branch or call instruction. If the branch instruction is not successful, then the program counter goes to the next ROM location within the current page.

In a successful call or branch execution the page address register (PA) receives its next page address from the buffer register (PB). The contents of the PB are changed by the load page instruction (LDP), which can be executed prior to the branch or call. Execution always continues on the same page unless PB is explicitly changed.

When the branch is executed successfully and when the processor is not in the call mode (CL = 0), the page buffer register is loaded into the page address register. If the contents of the page buffer register have been modified prior to the branch instruction, then this instruction is called a long branch instruction, since it may branch anywhere in the ROM (a long branch, BL, directive in the source program generates two instructions-LDP, load page buffer, and BR, branch). In the call mode (CL = 1), only "short" branches are possible, those staying within a given page.

Note that the normal state of the status logic is ONE. Several instructions can alter this state to a ZERO; however, the ZERO