A PDP-8 Implemented from AMD Bit-Sliced Microprocessors
An example of a microprogrammable system based on the Am2910 sequencer
and the Am2901 ALU will illustrate design with bit slices. The target machine
is the PDP-8 ISP (see Appendix 1 of Chap. 8). This register-transfer (RT)
level design of the micromachine is thus optimized toward the basic PDP-8.
However, the general principles involved in microprogramming bit slices
are illustrated by this example. A major goal of this design is the clarity
of implementation, rather than the economy of design.
The basic implementation is a one-stage pipeline as shown in Fig. 1 in Chap. 13. In this micromachine, the pipeline register stores the current microinstruction, which is being executed by the Am2910 Sequencer and the Am2901 ALU. The status information (zero, overflow, etc.) of the ALU operations is stored in the Status Register. In a one-stage pipeline design, conditional branches can be executed only by the microinstruction following the microcycle that has generated the branching status. The Am2910 sequencer is used instead of the Am2909 to simplify the design and to aid understandability. A more cost-effective design might actually result from using the Am2909 sequencer, since the number of microinstruction types used to emulate the PDP-8 is small. The Am2901 ALU is used because it more closely reflects the ISP of the PDP-8.
A timing diagram for a typical microcycle is shown in Fig. 1. The indicated delays are typical values, illustrating the timing requirements rather than actual component performances. On the rising edge of the system clock, the Pipeline Register latches the microinstruction to be executed during this microcycle. The output of the Pipeline Register is valid 15 us later. After another 15-ns delay, the Condition Code input to the Am2910 is valid. The microsequencer generates the next microaddress based on the current microinstruction and the Condition Code input. When the microprogram memory output is valid (approximately 130 ns after the rising clock edge), the microcycle can be restarted. Concurrently with the sequencer operation and microword fetch, the Am2901 ALU executes the operations specified by the microword in the Pipeline Register. The output of the ALU is
valid prior to the falling edge of the system clock. External registers,
such as the Memory Address Register (MAR) and the Status Register, use
the falling clock edge to latch results from the ALU output port. In this
design, the duty cycle of the system clock does not need to be symmetrical
at 50 percent.
RT-Level Implementation and the Microword Format
The RT-level implementation of the Am2900/PDP-8 is shown in Fig. 2 for the control part, and in Fig. 3 for the data part. The design can best be explained in conjunction with the microword format shown in Table 1. The ISPS description of the RT-level design is listed in Appendix 2. The following subsections discuss the meaning of each microword field and the associated RT-level components. For each microword field, there are three possible bit sizes: the number of bits normally required for the associated components, the minimum required for this PDP-8 application, and the actual field size used. The position of each field in the microword is defined in the ISPS description. The reason for inserting extra bits is to align the fields on octal boundaries, thus aiding the reading of the encoded microprogram.
Sequencer Instruction and Address Field
The Am2910 sequencer normally requires a 4-bit-wide instruction and a 12-bit-wide "next address" direct input. The microprogram occupies less than 128 words, requiring only 7 bits of address. Two extra instruction bits and two extra address bits are inserted as 0s in this design example for octal boundary alignment.
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