Table 9 Output and Internal Next-Cycle Register States for Am2909
 

Cycle	S1, S0, FE, PUP	m PC	REG	STK0	STKI	STK2	STK3	YOUT	Comment	Principal use
N N+1	0 0 0 0 . . . . . .	J J+1	K K	Ra Rb	Rb Rc	Rc Rd	Rd  Ra	J . . .	Pop stack	End loop
N N +1	0 0 0 1 . . . . . .	J J +1	K K	Ra J	Rb Ra	Rc Rb	Rd  Rc	J . . .	Push m PC	Setup loop
N N+1	0 0 1 X . . . . . . .	J J+1	K K	Ra Ra	Rb Rb	Rc Rc	Rd Rd	J . . .	Continue	Continue
N N + 1	0 1 0 0 . . . . . .	J K+ 1	K K	Ra Rb	Rb Rc	Rc Rd	Rd Ra	K ...	Pop stack; Use AR for address	End loop
N N + 1	0 1 0 1 . . . . . .	J K+ 1	K K	Ra J	Rb Ra	Rc Rb	Rd Rc	K ...	Push m PC; Jump to address in AR	JSR AR
N  N+ 1	0 1 1 X . . . . . . .	J  K + 1	K  K	Ra  Ra	Rb  Rb	Rc  Rc	Rd Rd	K . . .	Jump to address in AR	JMP AR
N N+1	1 0 0 0 . . . . . .	J Ra+1	K  K	Ra  Rb	Rb  Rc	Rc  Rd	Rd Rc	Ra ...	Jump to address in STK0; Pop stack	RTS
N N+1	1 0 0 1 . . . . . .	J Ra+1	K K	Ra J	Rb Ra	Rc Rb	Rd  Ra	R ...	Jump to address in STK0; Push m PC
N N + 1	1 0 1 X . . . . . . .	J Ra+ 1	K K	Ra Ra	Rb Rb	Rc Rc	Rd  Rd	Ra . . .	Jump to address in STK0	Stack ref (loop)
N N +1	1 1 0 0 . . . . . .	J D+1	K K	Ra Rb	Rb Rc	Rc Rd	Rd  Ra	D ...	Pop stack; Jump to address on D	End loop
N  N +1	1 1 0 1 . . . . . .	J  D +1	K  K	Ra  J	Rb  Ra	Rc  Rb	Rd  Rc	D . . .	Jump to address on D  Push m PC	JSR D
N N +1	1 1 1 X . . . . . . .	J D+1	K K	Ra Ra	Rb Rb	Rc Rc	Rd  Rd	D . . .	Jump to address on D	JMP D

X = Don't care, 0 = LOW, 1 = HIGH, Assume C_n = HIGH

Note: STK0 is the location addressed by the stack pointer.
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