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Microprogramming the IBM System/36O Model 301
Microprograms are sequences of microprogram words. A micro program word is composed of 60 bits and contains various fields which control the basic functions in the IBM System/360 Model 30 CPU. These basic functions are storage control, control of the data flow registers and the Arithmetic-Logic-Unit (ALU), micro program sequencing and branching control, and status bit-setting control. Microprogram words are stored in a Card Capacitor Read-Only Storage (CCROS) Fetching one microprogram word and executing it takes 750 nsec, the basic machine cycle.
Figure 1 shows in simplified form the data flow of the IBM System/360 (IBM 2030 CPU). It consists of a core storage with up to 65,536 8-bit bytes and a local storage (accessible by the microprogrammer but not explicitly by the 360 language program mer), a 16-bit storage address register (M, N), a set of ten 8-bit data registers (I, J, . . . , R), an arithmetic-logic-unit (ALU), connecting 8-bit wide buses (Z, A, B, M, N-bus), temporary registers (A, B), switches and gates.
Figure 2 shows the more important fields of a microprogram word. Only 47 bits are shown. Other fields contain various parity bits and special control bits. The field interpretation given in Fig. 2 is as for microprogram words in the second Read-Only Storage unit (Compatibility ROS) if the machine is equipped with the 1620 Compatibility Feature. The meaning of the microprogram word fields is explained in connection with Fig. 3 which shows the symbolic representation of a microprogram word together with an example as it appears on a microprogram documentation sheet.
The fields of the microprogram word can be grouped in five categories:
1 ALU control fields: CA, CF, CB, CC, CV, CD, CC
2 Storage control fields: CM, CU
3 Microprogram sequencing and branching fields: CN, CH, CL
4 Status bit setting field: CS
5 Constant field: CK
ALU control fields. On the line designated "ALU" in Fig. 3 an ALU statement can appear. It will specify an A-source and a B-source, possibly an A-source modifier and a B-source modifier, an operator, a destination, and possibly a carry-in control and a carry-out control.
CA is the A-source field. It controls which one of the 10 8-bit data registers is connected to the transient A-register and therefore to the A-input of the ALU
CB is the B-source field. It controls whether the R, L, or D-register or the C K-field is connected to the transient B-register and therefore to the B-input of the ALU. If "K" (CB = 3) is specified in this field, the A-bit constant field CK is doubled up; i.e., the same four bits are used as the high digit and the low digit.
Between the A-register and the ALU input is a straight/cross switch and a high/low gate. Its function is controlled by the CF-field. Depending on the value of this field, no input is gated into the ALU (Æ ) or only the low (L) or high digit (H) is admitted. CF = 3 gates all eight hits straight through, whereas the codes CF = 5, 6, and 7 cross over the two digits of the byte before admitting the low (XL) or high digit (XH) or both digits (X).
Between the B-register and the ALU input is a high/low gate and a true/complement control. The high/low gate is controlled by the CG-field in the same manner as the high/low gate in the A-input. The true/complement control is operated by the CV- field. It admits the true byte to the ALU (+) of the inverted byte (-) or controls a six-correct mechanism for decimal addition (@).
The operator and carry controls are given by the CC-field. This field specifies binary addition without carry handling (+0), addition with injection of a 1 (+ 1) (for instance, to stimulate subtraction in connection with the B-input inverter), addition with saving the carry in bit 3 of register S (+0,Save C, and +1,Save C), and addition using an old carry stored in bit 3 of register S and saving the new carry in this same bit (+C, Save C). Other codes specify logical operations (AND, OR, XOR).
The CD-field specifies into which register the result of the ALU operation is gated. Any one of the 10 data registers can be specified. Z means that the ALU output is gated nowhere and will be lost.
Storage control fields. On the line designated "storage" in Figure 3, a storage statement can appear. It will specify whether this microcycle is a ready cycle, a write cycle, a store cycle or a no-storage access cycle, and from where the storage address is supplied (CM-field) and whether storage access is to main storage or local storage (CU-field). Note that a full storage cycle (1.5 m sec) corresponds to two read-only storage cycles (750 nsec).
The codes CM = 3, 4, or 5 specify read cycles. The addresses are supplied from the register pairs IJ, UV, and LT, respectively. A read cycle reads 1 byte of data from core storage into the storage data register R.
A write cycle regenerates the data from the storage data register B at the address supplied in the last read cycle.
1Abstracted from Helmut Weber, "A Microprogrammed Implementation of EULER on IBM System/360 Model 30," Comm. ACM, vol. 10, no. 9, September 1967, pp. 549-558; material based on Fagg et al. , pp. 205-231. Figure 4 and related text by Siewiorek, Bell, and Newell.
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