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Introduction

This chapter introduces the reader to the LSPS notation. Although some details have been excluded, it covers enough of the language to provide a reading capability. Thus while this chapter in itself might not be sufficient to allow writing ISPS descriptions, it should be detailed enough to permit the reading and study of complex descriptions.

To describe the instruction-set processor (ISP) of a computer, or any machine, the operations, instructions, data-types, and interpretation rules used in the machine need to be defined. These are introduced gradually as the primary memory state, the processor state, and the interpretation cycle are described. Primary memory is not, in a strict sense, part of the instruction-set processor, but it plays such an important role in its operation that it is typically included in the description. In general, data-types (for example, integers, floating-point numbers, characters, and addresses) are abstractions of the contents of the machine registers and memories. One data-type that requires explicit treatment is the instruction, and the interpretation of instructions is explored in detail.

The PDP-8 ISPS description is a source of examples. In the presentation of the PDP-8 registers and data-types the following conventions will be used: (1) names in uppercase correspond to physical components on the PDP-8 (e.g., program counter and interrupt lines); (2) names in lowercase do not have corresponding physical components (e.g., implementation variables and instruction fields).

The description of the PDP-8 begins by specifying the primary memory that is used to store data and instructions: MP\Memory.Primary[0:4095]<O :11>,

The primary memory is declared here as an array of 4,096 words, each 12 bits wide. The memory has a name, MP, and an alias, Memory. Primary. Such aliases are a special form of comment and are useful for indicating the meaning or usage of a register's name. As in most programming languages, ISPS identifiers consist of letters and digits and begin with a letter. A period with no space following is also used to increase readability. The expression [0:4095] describes the structure of the array. It declares the size(4,096 words) and the names of the words (0,1,…., 4094,4095). The expression <0:11> describes the structure of each individual word. It declares the size (12 bits) and the names of the bits(0,1,….., 10,11).

It should be noted that bit and word names are precisely that: identifiers for the subcomponents of a memory structure. These names do not necessarily indicate the absolute position of the subcomponents. Thus, R<7:3> is a valid definition of a 5-bit register. The fact that the five bits are named 7, 6, 5, 4, and 3 should not lead to confusion with the seventh, sixth, etc., positions inside the register. Thus, bit 7 is the leftmost bit, bit 6 is located in the next position to its right, etc., while bit 3 is the rightmost bit.

Memory is divided into 128-word pages. Page zero is used for holding global variables and can be accessed directly by each instruction. Locations 8 through 15 of page zero have the special property called auto indexing, whereby when a location is accessed indirectly, the contents of the location are incremented by 1. These regions of memory can be described as part of M as follows:

page. zero [0: 127]<0: 11> := MP [0 : 127 ] <0 : 11>,
auto.index[0:7]<0: 11> := MP[8:15]<0:1l>,

The word-naming (and bit-naming) conventions on the left-hand side of a field declaration are independent of the word (bit) names used on the right-hand side: auto. index[0] corresponds to MP[8], auto.index[1] corresponds to MP[9], etc.

The processor state is defined by a collection of registers used to store data, instructions, condition codes, etc., during the instruction interpretation cycle.

The PDP-8 has a 1-bit register L, which contains the overflow or carry generated by the arithmetic operations, and a 12-bit register AC, which contains the result of the arithmetic and logic operations. The concatenation of L and AC constitutes an extended accumulator LAC. The structure of the extended accumulator is shown below:

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