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It is difficult to use the simplistic constant ratio measures across each level-of-interpretation when comparing machines of differing classes (e.g., micro to super) because there is no consistency of data-types (e.g., micros started out with no built-in real arithmetic at a time when minis included them). However, for machines within a class (e.g., mini) where the data-types are implied by the class name, simplistic comparison is probably all right, since the two machines most likely have about the same data-types. Hence a count of the number of data-types reflecting the built-in operations is one of the more significant architectural performance indicators, whether it be for a micromachine, macromachine, or a language machine.


The PMS structure, with the corresponding attributes determining performance (memory cycle time, processor execution rate), provides the basis for understanding machines and comparing them with each other. Figure 1 gives a PMS diagram of a basic computer, with the parameters that, to a first approximation, characterize performance. Alternatively, one might use a more descriptive, or tabular, form; but the goal is to provide a structural/performance basis for defining parameters and comparing and specifying the finite resources of the computer so that performance can be determined against actual workload.

It is imperative to consider the resource constraints and the effect of their interaction as each layer of a machine is designed. For example, a certain line printer requires buffer space (memory size) and central processing time which is then unavailable at the next machine level (e.g., FORTRAN).

Bell and Newell [1971:52] argued that a machine (at any level) can be described with any number of parameters, and carried out the exercise for up to five parameters (Table 1).

Information rate between the processor and memory is used as the processor speed indicator instead of the more conventional instructions per second. Compound indicators such as the product of processor speed times memory size to indicate basic computational performance were not allowed.

The example in Table 2 shows three different architectures with two implementations of a stack architecture. One has the stack in the primary memory (Mp), and the other assumes the stack is in the processor (Pc), using fast registers. The hardware implementations are held roughly constant (the processor to primary memory data rate) and the architecture is varied in order to compare the effect on performance. Note the difference in the various measures in what should fundamentally be about the same performance for a simple benchmark problem.

The statement execution rate (the actual performance) is the highest for the 3-address machine. In contrast, the conventional instructions per second measure shows the 3-address machine to have the lowest performance (by a factor of 4). A more subtle measure, operation rate, is correlated with the true benchmark statement execution rate. It should be noted (ignoring the first machine, a stack machine with stack top in primary memory) that the information rate is a good

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