An ISPS Primer for the Instruction Set Processor Notation
This appendix introduces the reader to the ISPS notation. Although some details have been excluded, it covers enough of the language to provide a "reading" capability. Thus, although the primer by itself might not be sufficient to allow writing ISPS descriptions, it should be detailed enough to permit the reading and study of complex descriptions. We use the PDP-8 ISPS description as a source of examples.
In the presentation of the PDP-8 registers and data-types the following conventions are used: (1) names in upper case correspond to physical components on the PDP-8 (e.g., program counter, interrupt lines, etc.); (2) names in lower case do not have correspondent physical components (e.g., instruction mnemonics, instruction fields, etc.).
INSTRUCTION SET PROCESSOR DESCRIPTIONS
To describe the instruction set processor (ISP) of a computer, or any machine, the operations, instructions, data-types, and interpretation rules used in the machine need to be defined. These are introduced gradually as the primary memory state, the processor state, and the interpretation cycle are described. Primary memory is not, in a strict sense, part of the ISP, but it plays such an important role in its operation that it is typically included in the description. In general, data-types (integers, floating-point numbers, characters, addresses, etc.) are abstractions of the contents of the machine registers and memories. One data-type that requires explicit treatment is the instruction, and the interpretation of instructions are explored in great detail.