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MULTI-MICROPROCESSORS: AN OVERVIEW AND WORKING EXAMPLE 465

or specialized run-time systems be developed to do this decomposition automatically or must the programmer do the decomposition explicitly?

2. Interconnection structures. What are the most effective types of processor/memory and processor/processor interconnection structures. and what are the related communication protocols?

3. Address mapping mechanisms. What mechanisms are appropriate for performing the virtual-to-physical address translation? These mechanisms should allow processors to share code and data while ensuring adequate levels of protection and performance.

4. Software system structure. What software structures are suitable for large systems containing hundreds of processors? Among the important problems in this area are resource management, software distribution, protection, and reliability.

5. Interprocessor interference. Even after tasks have been decomposed to run on multiple processors, how should inter- processor interference and contention for memory and I/O resources be minimized?

6. Deadlock avoidance. With multiple processors contending for resources, the potential exists for a situation where each of a group of processors is waiting for resources assigned to other processors in the group, and none of the processors in the group is able to proceed until its demands are satisfied. This situation, known as deadlock, effectively disables all the processors involved, and special care must be taken in the design to avoid it.

7. Fault tolerance. What hardware and software structures will allow a multi processor system to realize its potential for surviving the failure of components in the system?

8. Input/output. How should input/output devices in general, and secondary storage devices in particular, be integrated into a multi-microprocessor system?

The next section in this article surveys the spectrum of multiple-processor systems that are under active consideration and that hold some promise for becoming viable organizations for future computer systems. Given the relatively ill-defined nature of many of the unresolved questions listed above, the real potential and limitations of a multi-microprocessor architecture can only be understood by considering a specific system in depth. The section summarizing the architecture of the Cm* system, which has recently been developed at Carnegie-Mellon University (CMU), is presented to highlight some of the important considerations in implementing and programming a real multi processor system. The detailed design and implementation of Cm* are discussed in a re cent set of papers [Jones et al., 1977; Swan et al., 1977; Swan et al., 1977a[. The principal conclusions of the performance studies of Cm* are presented in the fourth section of this paper. The structure of the virtual addressing mechanism and the kernel operating system now running on Cm* are the subject of a paper by [Jones et al., 1978].

OVERVIEW OF MULTIPLE PROCESSOR STRUCTURES

There is currently no established methodology for interconnecting sets of processors for the purpose of building large, general purpose or even special purpose computer systems. However, there does exist an interesting range of possibilities and Figures 2 through 4 show three generic organizations that span this range:

computer networks, multiprocessors, and multiple arithmetic unit processors. Other taxonomies of multiple-processor systems have

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