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three have had considerable impact on performance. Attention here is focused mainly upon the CPU. Memory performance enhancements such as caching are considered only in so far as they affect CPU performance.

This paper is divided into two major parts. The first part presents an archetypal implementation followed by the model-specific variations from the archetype. These variations represent the design tradeoffs. The second part presents methodologies for determining the impact of various design parameters on system performance. The magnitude of the impact is quantified for several parameters and the use of the results in design situations is discussed.

The PDP- 11 Family is a set of small- to medium-scale stored program central processors with compatible instruction sets. The 11 Family evolution in terms of increased performance, constant cost, and constant performance successors is traced in Figure 1. Since the 11/45, 11/55 and 11/70 use the same processor, the KB11, only the 11/45 is treated in this study.


The broad middle range of PDP-11s have comparable implementations yet their performances vary by a factor of 2. The processors making up this group are the PDP-11/04, 11/l0,* 11/20, 11/34, 11/40, and 11/60. This section discusses the features common to these implementations and the variations found between machines which provide the dimensions along which they may be characterized.

Common Implementation Features

All PDP-l1 implementations, be they low, medium, or high performance, can be decomposed into a set of data paths and a control unit. The data paths store and operate upon byte and word data and interface to the Unibus, permitting them to read from and write to

Figure 1. PDP-11 Family tree.

memory and peripheral devices. The control unit provides all the signals necessary to evoke the appropriate operations in the data paths and Unibus interface. Mid-range PDP-11s have comparable data path and control unit implementations allowing them to be contrasted in a uniform way. In this section, a basis for com paring these machines is established and used to characterize them.

Data Paths. An archetype may be constructed from which the data paths of all mid range PDP-11s differ but minimally. This archetype is diagrammed in Figure 2. All major registers and processing elements as well as the links and switches which interconnect them are indicated. The data path illustrations for individual implementations are grouped with Figure 2 at the end of the chapter. These figures are laid out in a common format to encourage comparison. Note that with very few exceptions, all data paths are 16 bits wide (PDP-11 word size).

The heart of the data paths is the arithmetic logic unit or ALU through which all data circulates and where most of the processing actually takes place. Among the operations performed by the ALU are addition, subtraction, one's


*The 11/05 and the 11/10 are identical machines sold to different markets. This chapter refers to the machine as the 11/10.

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