A MINICOMPUTER-COMPATIBLE MICROCOMPUTER SYSTEM: THE DEC LSI-11 311

normal use by the program being debugged. The ASCII console routines also allow the user to boot load from a specified device in a byte transfer mode. All together, the ASCII console routines occupy about 340 words of microcode; since this space is available in the second MICROM, the console functions are made possible at no extra cost.

Real-Time Clock. Many low-end configurations require a real-time clock, driven by the power-line frequency or other timing signal, which is normally implemented with external control logic. To save this expense, such a device has been programmed into the LSI-l1 processor microcode. To use this clock, the user need only connect the timing signal to the processor through the bus line BEVNT. Once connected, this clock is identical to the KW-11L line clock when used in an interrupt mode, except that it may not be turned on and off. An optional jumper disables the real-time clock if its operation is not desired.

One disadvantage of using dynamic MOS memories is the necessity of refreshing their contents at appropriate intervals. This refresh operation is needed to replace the stored charge in each memory cell which has been lost through leakage current. In typical dynamic MOS memories, each cell must be refreshed every 2 milliseconds. Most dynamic memories are implemented in such a way that any normal memory access refreshes a group of cells (or "row") on all selected memory chips. One access must then be made to each row of every memory chip; the 4 K memories used in the LSI-l1 system require that 64 accesses be made. Normally, the logic to control the refresh operation would include a 6-bit counter, a clock, and memory access arbitration circuitry.

In order to minimize this control circuitry, the LSI-l 1 CPU microcode features automatic refresh control. When enabled by an optional jumper, the CPU takes a refresh trap approximately every 1.6 ins. At this time, it performs 64 memory references while asserting a special bus signal, BREF. This signals all dynamic memories to cycle at the same time. Direct Memory Access (DMA) requests are arbitrated between bus refresh cycles to reduce DMA latency. External interrupts, however, are locked out during the burst refresh time, temporarily increasing interrupt latency. (When this latency can not be tolerated, external refresh circuitry can drive the bus and assert BREF, allowing use of either refresh method with the same memory modules.) The automatic refresh feature is not needed, of course, in systems without dynamic memories.

Power-Fail/Restart Options. The flexibility of the LSI- 11 system is further enhanced by the availability of several power-fail/restart options. The power-fail sequence, which is normally of use only with nonvolatile main memory, is compatible with other members of the PDP-l1 family. Upon sensing a warning signal from the power supply, the power-fail trap is taken. The current PSW and PC are pushed on the processor stack, and a new PC and PSW are taken from a vector at octal location 24. Normally, the routine thus invoked would save processor registers, set up a restart routine, and HALT. When volatile memory is used, the register may not be saved; in this case, the power- fail trap allows an orderly system shut-down to occur.

Four power-up options are selected by two jumpers on the LSI- 11 CPU module. The first of these is to load a previously set-up PSW and PC from the vector at location 24. Normally used with nonvolatile memory to continue execution from the power-fail point, this option is compatible with the normal PDP-l1 power- up sequence. If ROM program storage is employed, this option allows the program to be started at an arbitrary address. If the BHALT line on the bus (the HALT switch) is asserted during this power-up sequence, the console microcode will be entered immediately after loading the PSW and PC.