232 THE PDP-11 FAMILY
4. Several data-type extensions were not predicted. Although floating-point arithmetic was envisioned, the character string and decimal operations were not envisioned, or at least were not described. These data-types evolved in response to market needs that did not exist in 1970.
CONCEPTUAL BASIS FOR THE PDP-11 MODELS
Chapters 10 and 11 consist of two papers that form some of the conceptual basis for the various PDP-11 models. Chapter 10 by Strecker is an exposition of cache memory structure and its design parameters. The cache memory concept is the basis of three PDP-l1 models, the PDP-l l/34A, the PDP-l1/60, and the PDP-l1/70, in addition to the cache-8 (Chapter 7) and the KL10 processor for the PDP-l0 (Chapter 21).
Strecker gives the performance evaluation in terms of cache miss ratios, whereas the reader is probably interested in performance or speedup. These two measures, shown in Figure 1, are related [Lee, 1969] in the following way (assuming an infinitely fast processor):
p = Total number of memory accesses by the processor Pc
m = Number of memory accesses that are missed by the cache and have to be referred to the primary memory Mp
t.c = Cycle time of cache memory Mc
t.p = Cycle time of primary memory Mp
R = t.p/t.c (ratio of memory speeds), where R is typically 3 to 10
The relative execution speeds are:
t (no cache) = pR
t (to cache) = p + mR
speedup = pR/(p + mR) = R/(1 + (m/p) R)
a = miss ratio = m/p
Therefore:
speedup = R/(l + aR) = l/(a + l/R)
Note that:
If a = 0 (100% hit), the speedup is R
If a = 1 (100% miss), the speedup is R/(1 + R), i.e., the speedup is less than 1 (i.e., time to reference both memories)
Chapter 11 contains a unique discussion of buses - the communications link between two or more computer system components. Although buses are a standard of interconnection, they are the least understood element of computer design