160 BEGINNING OF THE MINICOMPUTER
tested on a jig. The cabling was reduced to one console cable, one teleprinter cable, one I/O bus cable assembly, and two memory bus cables. In trying to limit console cabling, a time division multiplex communication scheme was designed to get the signals to the lights and from the switches. In this scheme, a number of signals were transmitted on the same wires on a timeshared basis, and the console lamp filaments were used as storage elements. While this scheme was clever enough to gain the PDP-15's only patent, it was generally unsatisfactory. It made the console logic so complex that when it failed, it was harder to fix than the processor.

The goal of reducing interrupt latency to two microseconds was not achieved. With the parity, memory protect, and memory relocation options implemented, and with adder and synchronizing delays added in, the latency could only be reduced to four microseconds; but that was acceptable.

The goal of packaging the basic system (central processor, I/O processor, console, and 32 Kwords) in one cabinet was met; it was a close fit, and there were virtually no spare module slots. Since few small systems were sold, it is not clear that this emphasis was warranted.

The goal of extended I/O bus length was achieved by switching from an unterminated, diode-clamped I/O bus such as the PDP-9 used, to a new, terminated I/O bus. A new set of bus transceiver modules was designed to provide greater speed and less bus loading. The new bus design, with cleaner signals and no reflections, combined with the new bus transceiver modules, permitted the I/O bus to be extended to 75 feet. The penalty paid was higher power consumption and greater power supply cost than in the PDP-9.

The goal of better maintainability was partially achieved by equipping the logic with a means of monitoring 400 signal points. This feature was combined with a single step feature which permitted troubleshooting from the console without the use of an oscilloscope. As it turned out, the single step feature was used in frequently because of the training required to use it properly.

Figure 31 shows the register transfer structure of the PDP-15 processor. It was based on elements and features used in earlier designs and had a basic data path which permitted the results from any of the 11 registers to be read into the arithmetic unit and then back into the registers. In order to achieve high speed operation, a number of separate registers (such as the Step Counter, the Program Counter, and the Multiplier-Quotient registers), operated in