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that formed the basis of the PDP- 1 were directly patterned after the circuits of the TX-0 and the TX-2 computers at M.I.T., as discussed in Chapter 5.

The TX-O and TX-2 computers were among the most advanced machines of their time and were the offspring of M.I.T.'s Whirlwind [Everett, 1951; Redmond and Smith, 1977], a computer that was operational in 1950. Whirlwind (Figure 1) was an important ancestor of the TX-0, the PDP-1, and modern minicomputers because of the short word length (16 bits), because of the high speed operation, and because of the people involved in its development. The high speed operation was accomplished by using an M.I.T.-developed random-access storage tube rather than a drum for primary memory. Subsequently, performance was further upgraded by using the core memory that was developed by Jay Forrester at M.I.T. in 1951 [Forrester, 1951]*

To test the Whirlwind core memory, a special computer called the Memory Test Computer (MTC) was developed by a design team headed by Ken Olsen, a recent M.I.T. graduate. The core memory worked so well that it was immediately moved to Whirlwind. A 4-Kword memory was built for MTC, permitting MTC to be operated as a special purpose computer for several years.

MTC is shown in Figure 2 as it was first assembled and operated in a factory building near M.I.T. Its word length was selected to be 16 bits because that was the size of the Whirlwind memory being tested and because 16 bits were adequate to represent the data for M.I.T.'s Project Lincoln air defense applications.

The MTC turned out to be a useful training ground for the designers (especially K. Olsen) when they went to Project Lincoln's new facility, Lincoln Laboratory in Lexington, Massachusetts. The MTC packaging, circuits, and toggle switches influenced the subsequent TX-0 design. The MTC packaging used various standard radio relay racks and had a somewhat homely appearance; this encouraged the designers to be more concerned about appearance in the future. The MTC circuits used significantly smaller modules than those in Whirlwind and used a gated pulse delay line clock for control rather than the synchronous clock used in Whirlwind. In addition, MTC used a dc bus for gating registers to one another that was carried out on an open-wired bus (versus coaxial cable) that ran the entire length of the computer. The MTC toggle switches formed a memory of 32 registers. As it turned out, when the 512 toggle switches were put together, they formed about the most unreliable part of the computer. At the time, lifetesting in large batches was not done; hence, the experience with the MTC toggle switches formed the basis for significant improvement of switch designs in the TX-0.

Although the speed of the MTC was about the same as the speed of Whirlwind, it was not fully used, perhaps because it lacked the software and peripherals.

Like the MTC, the TX-0 was designed as a test device. It was designed to test transistor circuitry, to verify that a 256 X 256 (64-Kword) core memory could be built [Mitchell and Olsen, 1956] and to serve as a prelude to the construction of a large-scale 36-bit computer, the TX-2. The transistor circuitry being tested featured the new Philco SBT100 surface barrier transistor, costing $80, which greatly simplified transistor circuit design. The work on the 256 X 256 core memory, using vacuum-tube drivers,


* Whirlwind was dismantled in 1959 and moved to Wolf Research and Development where it was reassembled and operated until the 1970s. Whirlwind is now part of the Digital Distributed Museum Project, although the first core memory module and other parts have been given to the British Science Museum, the Smithsonian. and other museums.

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