Benjamin Lee is broadly interested in power-efficient, high-performance computer architectures (e.g., adaptive uniprocessors, heterogeneous multiprocessors, accelerators) and applications (e.g., numerical methods, scientific computing). He is also interested in analytics, statistical inference, and machine learning methodologies that enable qualitatively new studies in these areas.

Current Research

Statistical inference enables fundamentally new capabilities for capturing relationships within parameter spaces for microarchitectures [ASPLOS'06]. The computational efficiency of statistical inference not only provides answers to prior questions far more quickly, it also provides new answers to much larger, previously intractable questions. Lee proposes a microarchitectural simulation paradigm that defines a comprehensive design space, simulates sparsely sampled design points, and derives inferential models to reveal trends. These models are inexpensively constructed, efficient, and accurate surrogates for simulators of multi-billion point design spaces.

Moreover, inference is equally applicable to both sides of the hardware/software interface, whether estimating the impact of process variations in emerging circuit technologies (e.g., 3T1D memories [TR'08]) or estimating performance scalability for tunable parallel applications (e.g., LINPACK, Multigrid [PPoPP'07]).


The computational efficiency of inference closes the divide between detailed simulation and best known practices in classical optimization, which Lee applies to microarchitectural performance, power and temperature. Pareto frontiers and contour maps for large, comprehensive design spaces are now possible. Iterative optimization heuristics become tractable when predictive regression models replace simulation within the iterative loop. Thus, efficient surrogates for detailed simulation allow designers to leverage the wealth of literature and history in classical optimization for qualitatively new studies of performance-power efficiency [HPCA'08], multiprocessor heterogeneity [HPCA'07], and microarchitectural adaptivity [ASPLOS'08].


The computational efficiency of statistical inference enables qualitatively new capabilities in multiprocessor analysis. Further reducing multiprocessor simulation costs, Lee proposes composing uniprocessor performance models with multiprocessor contention/penalty models [MICRO'08]. This composition leverages information captured by relatively inexpensive uniprocessor analysis, significantly reducing required multiprocessor simulations to only the few needed for predicting contention and associated penalties. Lee combines this approach with statistical inference, to enable advanced pathfinding studies for both homogeneous [HPCA'06] and heterogeneous [HPCA'07] multiprocessor design.


Lee is interested in environmentally sustainable digital practices and technologies [StGallen'07]. Increasing centralization of compute resources, driven by the commoditization of compute servers and economies of scale, suggests environmental and energy effects from IT infrastructure are most effectively monitored in and optimized for large-scale data centers. Equally important is a comprehensive assessment of trends in technology adoption. Validating claims of net environmental benefits from the adoption of digital business practices, researchers must assess the degree to which technology is an incomplete substitute for traditional business practices. Future research in digital sustainability will span fundamental technology, business management, and public policy [StGallen'08].

Lee worked to optimize sparse matrix-vector multiply (SpMV), constructing heuristics that automatically tune linear algebra computational kernels to reflect the capabilities of current compiler and hardware technologies [SC'02]. In particular, Lee implemented and examined optimizations for symmetric SpMV including algorithmic, data structure, compiler, and architecture-specific optimizations. These optimizations exploit the symmetric structure of the matrix to improve performance by as much as 2.6x while reducing storage costs and memory traffic by 0.5x [ICPP'04]. This implementation of symmetric SpMV is incorporated into published libraries, which use heuristics to search for the best choice of values for tunable parameters [OSKI]. Furthermore, Lee constructed models to estimate upper bounds on performance as a function of system and algorithmic parameters, thereby evaluating the effectiveness of optimizations against theoretical peak performance.