An instruction fetch unit for a high-performance personal computer

Butler Lampson, Gene McDaniel, and Severo Ornstein

 

Citation: IEEE Trans. Computers C-33, 8 (Aug. 1984), pp 712-730.

Links: Abstract, Acrobat. Here is an HTML version created by OCR for the benefit of search engines; it is not meant for human consumption.

Email: blampson@microsoft.com. This paper is at http://www.research.microsoft.com.

 

Abstract:

The instruction fetch unit (IFU) of the Dorado personal computer speeds up the emulation of instructions by prefetching, decoding, and preparing later instructions in parallel with the execution of earlier ones. It dispatches the machineís microcoded processor to the proper starting address for each instruction, and passes the instructionís fields to the processor on demand. A writable decoding memory allows the IFU to be specialized to a particular instruction set, as long as the instructions are an integral number of bytes long. There are implementations of specialized instruction sets for the Mesa, Lisp, and Smalltalk languages. The IFU is implemented with a six-stage pipeline, and can decode an instruction every 60 ns. Under favorable conditions the Dorado can execute instructions at this peak rate (16 mips).