A Processor for a High-Performance Personal Computer

Butler W. Lampson and Kenneth A. Pier


Citation: Proc. 7th IEEE Symposium on Computer Architecture, La Baule, France, 1980, pp146-160. Reprinted in 25 years of the International Symposia on Computer Architecture (selected papers), 1998, pp 180-194.  Also in Technical Report CSL?81?1, Xerox Palo Alto Research Center.

Links: Abstract, Acrobat as published, Acrobat (produced by scanning and OCR, with some errors), Word, Web page

Email: blampson@microsoft.com. This paper is at http://www.research.microsoft.com.



This paper describes the design goals, micro-architecture, and implementation of the microprogrammed processor for a compact high performance personal computer. This computer supports a range of high level language environments and high bandwidth I/O devices. Besides the processor, it has a cache, a memory map, main storage, and an instruction fetch unit; these are described in other papers. The processor can be shared among 16 microcoded tasks, performing microcode context switches on demand with essentially no overhead. Conditional branches are done without any lookahead or delay. Microinstructions are fairly tightly encoded, and use an interesting variant on control field sharing. The processor implements a large number of internal registers, hardware stacks, a cyclic shifter/masker, and an arithmetic/logic unit, together with external data paths for instruction fetching, memory interface, and l/O, in a compact, pipelined organization.

The machine has a 50 ns microcycle, and can execute a simple macroinstruction in one cycle; the available I/O bandwidth is 640 Mbits/set. The entire machine, including disk, display and network interfaces, is implemented with approximately 3000 MSI components, mostly ECI, 10K; the processor is about 35% of this. In addition there are up to 4 storage modules, each with about 300 16K or 64K RAMs and 200 MSI components, for a total of 8 Mbytes. Several prototypes are currently running.