About Software Radio
In conventional wireless communication systems, the critical lower layer processing, that is, the physical layer (PHY) and medium access control (MAC), is typically implemented in hardware (ASIC chips), due to the high-computational and real-time requirements. Designing ASIC is costly, both economically and time-wise. It is also fixed, and therefore, once it is delivered, it cannot be changed or upgraded. The lack of flexibility and programmability makes experimental research in wireless communication become very difficult, especially for research groups in academics.
Software Radio (or Software Defined Radio, SDR) holds the promise of fully programmable wireless communication systems, effectively supplanting current technologies that have the lowest communication layers implemented primarily in fixed, custom hardware circuits. It is an engineering dream that one day, all wireless functions will be implemented completely in software. Indeed, researchers and engineers have been making progress in this direction and has been constantly pushing the hardware-software boundary in wireless communications.
Platform Dilemma (c. 2005 - c. 2010)
Today, software radio developers are facing a platform dilemma. Many current SDR platforms are based on either programmable hardware, such as field programmable gate arrays (FPGAs), or embedded digital signal processors (DSPs). Such hardware platforms can meet the processing and timing requirements of modern high-speed wireless protocols, but programming FPGAs and specialized DSPs are difficult tasks. Developers have to learn how to program to each particular embedded architecture, often without the support of a rich development environment of programming and debugging tools. Hardware platforms can also be expensive.
In contrast, SDR platforms based on general-purpose processor (GPP) architectures, such as commodity PCs, have the opposite set of tradeoffs. Developers program to a familiar architecture and environment using sophisticated tools, and radio front-end boards for interfacing with a PC are relatively inexpensive. However, since PC hardware and software have not been designed for wireless signal processing, existing GPP-based SDR platforms can achieve only limited performance. For example, the popular GNU Radio/USRP platform achieves only a few hundred Kbps throughput on an 8MHz channel, whereas modern high-speed wireless protocols like 802.11 support multiple Mbps data rates on a much wider 20MHz channel. These constraints prevent developers from using such platforms to achieve the full fidelity of state-of-the-art wireless protocols while using standard operating systems and applications in a real environment.
The Sora Approach
Microsoft Research has provided a solution to this platform dilemma by developing Microsoft Research Software Radio (Sora), a fully programmable software radio platform that provides the benefits of both SDR approaches. It is based on software running on a low-cost, commodity PC with a general purpose OS (like Windows).
We take a multi-core PC, plug in a PCIe radio control board we developed, and hook up a third-party radio front-end with antenna -- that becomes a powerful software radio platform. The PC interface board takes the I/Q signals from the RF front-end and puts them into the PC memory as fast as possible (via DMA). It also takes the software-generated waveforms (outgoing I/Q signals) from PC memory and pushes them through the RF front-end at the right timing. No baseband signal processing takes place in hardware. All is left to the software running in the PC.
The PC runs a normal operating system (Microsoft Windows) with the Sora drivers and SDK installed. The Sora software stack manages all aspects of the radio hardware and provides an environment for the programmers to manipulate the I/Q signals in main memory directly. The programmers can write any baseband signal processing software freely, usually in C language. The Sora software stack manages the system resources and enforces the real-time requirements. Additional software development tools and common signal processing libraries are also included in the Sora software package.
This provides a convenient way for experimenting with novel wireless technologies. With Sora, developers can implement and experiment with high-speed wireless protocol stacks (e.g., IEEE 802.11) by using commodity general-purpose PCs. Developers program in familiar programming environments with powerful tools on standard operating systems. Software radios implemented on Sora appear like any other network device, and users can run unmodified applications on their software radios with the same performance as commodity hardware wireless devices.
Technical Details (c. 2009)
To develop such a high-speed wireless platform on general-purpose PC architectures is very challenging:
- Transferring high-fidelity digital waveform samples into PC memory for processing requires very high bus throughput. Existing GPP platforms like GNU Radio (USRP) use USB 2.0 or Gigabit Ethernet, which cannot satisfy this requirement for high-speed wireless protocols.
- Physical layer (PHY) signal processing has very high computational requirements for generating information bits from waveforms, and vice versa, particularly at high modulation rates; indeed, back-of-the-envelope calculations for processing requirements on GPPs have instead motivated specialized hardware approaches in the past.
- Wireless PHY and media access control (MAC) protocols have low-latency real-time deadlines that must be met for correct operation. For example, the 802.11 MAC protocol requires precise timing control and ACK response latency on the order of tens of microseconds. Existing software architectures in the PC cannot consistently meet this timing requirement.
Sora uses both hardware and software techniques to address the challenges of using PC architecture for high-speed SDR:
- We have developed a new, inexpensive radio control board (RCB) with a radio frontend for transmission and reception. The RCB bridges an RF front-end with PC memory over the high-speed and low-latency PCIe bus. With this bus standard, the RCB can support 16.7Gbps (x8 mode) throughput with sub-microsecond latency, which together satisfies the throughput and timing requirements of modern wireless protocols while performing all digital signal processing on the host CPU and memory.
Radio control board provides a high-speed PCIe interface to host PC.
- To meet PHY processing requirements, Sora makes full use of various features of widely adopted multi-core architecture in existing GPPs. The Sora software architecture also explicitly supports streamlined processing that enables components of the signal processing pipeline to efficiently span multiple cores
- We change the conventional implementation of PHY components to extensively take advantage of lookup tables (LUTs), trading off computation for memory. These LUTs substantially reduce the computational requirements of PHY processing, while at the same time taking advantage of the large, low-latency caches on modern GPPs.
- Sora uses the SIMD (Single Instruction Multiple Data) extensions in existing processors to further accelerate PHY processing. With these optimizations, Sora can fully support the complete digital processing of 802.11b modulation rates on just one core (2GHz Intel x86), and 802.11a/g on two cores.
- To meet the real-time requirements of high-speed wireless protocols, Sora provides a new kernel service, core dedication, which allocates processor cores exclusively for real-time SDR tasks. We demonstrate that it is a simple yet crucial abstraction that guarantees the computational resources and precise timing control necessary for SDR on a GPP.
The Microsoft Research Asia team has developed a demonstration radio system, SoftWiFi, based on the Sora platform. SoftWiFi currently supports the full suite of 802.11a/b/g modulation rates, seamlessly interoperates with commercial 802.11 NICs, and achieves equivalent performance as commercial NICs at each modulation. Sora is the first SDR platform that enables users to develop high-speed wireless implementations, such as the IEEE 802.11a/b/g PHY and MAC, entirely in software on a standard PC architecture.
- Kun Tan, Jiansong Zhang, Ji Fang, He Liu, Yusheng Ye, Shen Wang, Yongguang Zhang, Haitao Wu, Wei Wang, and Geoffrey Voelker, "Sora: High Performance Software Radio using General Purpose Multi-core Processors," USENIX NSDI 2009, Apr 2009, Boston, MA. (Awarded Best Paper)
- Kun Tan, Jiansong Zhang, Ji Fang, He Liu, Yongguang Zhang, and G. M. Voelker, "Sora: High-performance Software Radio Using General-Purpose Multi-core Processors," Communications of the ACM, 54(1), January 2011.
- Sora: High Performance Software Radio Using General Purpose Multi-core Processors. In NSDI 2009, Boston, Massachusetts, USA, Apr 2009. (Awarded Best Demo)
- Soft-LTE: A Software Radio Implementation of 3GPP Long Term Evolution Based on Sora Platform. In ACM MobiCom 2009, Beijing, China, Sep 2009. (Honorable Mentioned Demo)
- Experimenting Software Radio with the Sora Platform. In SIGCOMM 2010, New Delhi, India, Sep 2010.
|Sora WiFi Demo (Jan 2011)