Although FPGAs have many unique advantages over other computing platforms, they have yet to gain widespread popularity. Two reasons for this is that many of the necessary development tools are very primative and that most of fundamental issues that FPGAs raise are poorly understood. We are investigating the obstacles that FPGAs must overcome for them to become practical, deployable systems.
Application Specification and Verification
The correctness of hardware and software systems can be verified via the use of PSL (Property Specification Language). Our group has investigated two aspects of the verification process. First, we have looked at the automatic translation of PSL specifications into monitoring circuits. This allows for online, zero-performance-overhead model checking. Second, we have looked at the automatic generation of PSL specifications based upon simulation traces. This tool can either be used to locate bugs or to fill in insufficient system specifications.
- Wenchao Li and Alessandro Forin, Specification Mining for Digital Circuits with Applications on Verification and Diagnosis, no. MSR-TR-2009-114, 21 August 2009
- Gabe Knezek, Richard Neil Pittman, and Alessandro Forin, Space-Efficient Implementation of P2V Monitors, no. MSR-TR-2008-117, August 2008
- Hong Lu and Alessandro Forin, The Design and Implementation of P2V, An Architecture for Zero-Overhead Online Verification of Software Programs, no. MSR-TR-2007-99, August 2007
Hardware Communication APIs
The communication interface between an FPGA and a host machine is generally critical, both from the standpoint of performance and development effort. Unfortunately, the existing options for implementing this interface are relatively limited. Designers can either choose:
1. the very low-level mechanisms provided by FPGA vendors. In this case, they face a complex and error-prone engineering task. Furthermore, the end results will likely not be portable to other systems.
2. find a company that provides a high-level communication scheme. However, these solutions are likely costly, closed-source and, again, specific to a particular device.
To provide a third alternative, we are attempting to build the first high-level, open-source FPGA communication API for use with Windows machines. This API, called Simple Interface for Reconfigurable Computing (SIRC) completely separates the communication mechanism, the user’s software code, and the user’s hardware logic. Such a system offers users the greatest level of portability and accessibility. So far, we support communication via Gigabit Ethernet. PCI Express support is currently under development and will be available soon.
We have also built an FPGA/SATA communication interface called Groundhog. This system offers FPGA application developers a very simple and easy-to-use way of directly accessing permanent storage such as hard drives and solid-state drives. We welcome users of Groundhog to contribute back to the open-source project, including feedback, testing, and support information for a wide variety of storage devices.
Tools and Systems for Dynamic Reconfiguration
A defining characteristic of FPGAs is their capability to quickly program themselves with different circuits. When used to dynamically reconfigure the system while it is in use, this feature can provide necessary capabilities such as resource virtualization and power savings. In practice, though, very few developers make use of this capability.
Largely, this is because dynamic reconfiguration is poorly supported and poorly understood. Our group has made efforts to implement systems to perform dynamic reconfiguration and explore its full potential.
- Ken Eguro, Automated Dynamic Reconfiguration for High-Performance Regular Expression Searching, in International Conference on Field-Programmable Technology (short paper), December 2009
- Shaoshan Liu, Richard Neil Pittman, and Alessandro Forin, Minimizing Partial Reconfiguration Overhead with Fully Streaming DMA Engines and Intelligent ICAP Controller, no. MSR-TR-2009-150, September 2009
- Shaoshan Liu, Richard Neil Pittman, and Alessandro Forin, Energy Reduction with Run-Time Partial Reconfiguration, no. MSR-TR-2009-2017, September 2009
- Jeff Carver, Richard Neil Pittman, and Alessandro Forin, Relocation and Automatic Floor-planning of FPGA Partial Configuration Bit-Streams, no. MSR-TR-2008-111, August 2008
The days in which FPGAs are relegated to simple glue-logic modules are long past. Today's reconfigurable devices are large and can implement sophisticated systems. However, these new capabilities also come with new responsibilities and we believe that the security considerations of FPGAs have largely been ignored thus far. We have investigated low-level issues such as physical security concerns and high-level issues such as access control isolation/permissions checking.
- Arvind Arasu, Ken Eguro, Raghav Kaushik, Donald Kossmann, Ravi Ramamurthy, and Ramarathnam Venkatesan, A Secure Coprocessor for Database Applications, in 23rd International Conference on Field Programmable Logic and Applications (FPL), September 2013
- Ken Eguro and Ramarathnam Venkatesan, FPGAs for Trusted Cloud Computing, in International Conference on Field-Programmable Logic and Applications, IEEE, August 2012
- Ji Sun, Ray Bittner, and Ken Eguro, FPGA Side-Channel Receivers, in International Symposium on Field-Programmable Gate Arrays (Best Paper Award - Honorable Mention), February 2011
- Richard Neil Pittman and Alessandro Forin, A Security Model for Reconfigurable Microcomputers, no. MSR-TR-2008-121, September 2008