Achieving the right balance of power and performance for an application is challenging with today's multicore processors. E2 solves this problem by providing the capability for cores to dynamically adapt their resources during execution to provide highly efficient power/performance hardware configurations for a wide range of workloads.
Explicit Data Graph Execution
At the heart of E2 is an advanced Explicit Data Graph Execution (EDGE) instruction set architecture (ISA), which unlike conventional ISAs:
- Encodes the data dependencies between instructions, freeing the microarchitecture from rediscovering these dependencies at runtime, and
- Groups instructions into atomic blocks (similar to transactions), providing a larger unit of work, and allowing the microarchitecture to tolerate growing wire delays
These two ISA features enable E2 to utilize a dataflow execution model, providing power-efficient out-of-order execution.
Current multicore systems provide a fixed and rigid computational substrate. In E2, physical cores are dynamically composable into powerful logical processors, allowing a single chip to tailor itself to the computational needs of a wide range workloads. E2 is configurable to provide:
- Many physical cores working independently,
- Many physical cores working in parallel to perform the same operations on multiple data sets simultaneously,
- Many physical cores composed together to form logical processors to accelerate single-threads of execution.
Core fusion allows E2 to span a wide power/performance spectrum, from power-efficient embedded processors to high-performance server class processors.
- Milovan Duric, Oscar Palomar, Aaron Smith, Milan Stanic, Osman Unsal, Adrian Cristal, Mateo Valero, Doug Burger, and Alex Veidenbaum, Dynamic-Vector Execution on a General Purpose EDGE Chip Multiprocessor, in IEEE International Conference on Embedded Computer Systems: Architectures, Modeling and Simulation (SAMOS), July 2014
- Milovan Duric, Oscar Palomar, Aaron Smith, Osman Unsal, Adrian Cristal, Mateo Valero, and Doug Burger, EVX: Vector Execution on Low Power EDGE Cores, in Design, Automation and Test in Europe (DATE), 9 March 2014
- Behnam Robatmili, Dong Li, Hadi Esmaeilzadeh, Sibi Govindan, Aaron Smith, Andrew Putnam, Doug Burger, and Stephen Keckler, How to Implement Effective Prediction and Forwarding for Fusable Dynamic Multicore Architectures, in 19th IEEE International Symposium on High Performance Computer Architecture (HPCA), February 2013
- Andrew Putnam, Aaron Smith, and Doug Burger, Dynamic Vectorization in the E2 Dynamic Multicore System, in 1st International Workshop on Highly-efficient Accelerators and Reconfigurable Technologies, June 2010
- Yanqi Zhou, Princeton, 2014
- Dan Zhang, The University of Texas at Austin, 2014
- Mehrzad Samadi, University of Michigan, 2011, 2013
- Milovan Duric, Technical University of Catalonia, 2013
- Raghuraman Balasubramanian, University of Wisconsin-Madison, 2012
- Ali Bakhoda, University of British Columbia, 2012
- Svilen Kanev, Harvard University, 2011
- Niket Choudhary, North Carolina State University, 2011
- Dai Bui, University of California, Berkeley, 2011
- Nathaniel McVicar, University of Washington, 2011
- Dong Li, The University of Texas at Austin, 2011
- Behnam Robatmili, The University of Texas at Austin, 2011
- Alexander Shalimov, Moscow State University, 2010